Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.

此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。

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If this value is negative, the clock time is set back at the start of daylight saving time and advanced at the end.

如果此值为负值，则时钟时间会在夏时制开始时向后调整，而在夏时制结束时向前调整。

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If this value is negative, the clock time is set back at the start of daylight saving time and advanced at the end.

如果此值为负值，则时钟时间会在夏时制开始时向后调整，而在夏时制结束时向前调整。

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