The design technique for a CMOS four quadrant analog multiplier is presented, which is based on the characteristics of the MOSFET subthreshold region.
讨论了基于MOS晶体管亚阈值区特性的CMOS四象限模拟乘法器的设计。
With the help of word-based modular multiplication algorithm, the proposed multiplier is able to work with any precision of the input operands.
设计中采用了按字运算的模乘算法，使本设计具有很好的可扩展性，它可以完成任意位数的模乘运算。
Based on a preliminary study on the identified multiplier method, it is pointed out in this paper that this method is a unite method of functional transformation in variational principle.
本文通过对已识别拉氏乘子法的初步探讨，指出了已识别拉氏乘子法是变分原理中泛函变换的统一方法。
The harmonic analysis with the FFT processing nucleus based on the internal hardware multiplier is analyzed in detail.
给出了系统硬件结构，对以内部硬件乘法器为FFT处理核的谐波分析技术进行了详细分析。
Through the finite domain multiplier design based on the polynomial multiplication theory in finite domain, a new simple multiplication algorithm in finite domain is introduced.
采用基于有限域中多项式乘法理论的快速有限域乘法器的设计，得到了简单的有限域上乘积运算算法。
In this thesis, the design and FPGA implementation result of a finite field polynomial multiplier is presented, whose arithmetic architecture is based on the number theoretic transform.
研究设计了一种具有自主知识产权的高速、高精度的有限域多项式相乘运算核。
The design and performance of multiplier with concurrent structure based on large scale integrated circuits technique are discussed in detail.
着重讨论了以大规模集成电路为基础的并发结构数字乘法器的设计和性能。
Based on many years 'teaching experience, the working principle and application of analogue multiplier are presented by popular, easy to understand and image mode.
基于多年的教学经验心得，将模拟乘法器的工作原理及应用，以通俗、易懂、形象的方式展现出来。
Model checking based on decision diagram causes memory explosion in integer multiplier verification. An efficient solution to this problem is backward substitution method.
采用基于决策图的模型检验方法对整数乘法器验证时会出现内存爆炸，解决该问题的一种有效途径是采用反向替换方法。
A new design method of pipelined multiplier for double precision floating point data based on IEEE754 standard was proposed.
提出了一种基于IEEE754标准的双精度浮点乘法器的流水线设计方法。
Three improved fast multiplier algorithms based on traditional Booth: Fully Redundant Booth, Partially Redundant Booth, Booth with Bias are analysed and evaluated in this thesis.
分析并评价了在传统贝斯算法基础上改进的几种算法，它们分别是完全冗余贝斯算法、局部冗余贝斯算法，以及有偏差的贝斯算法。
A project to design a power direction relay, which is based on an analog multiplier and an analog integrator, is presented in this paper.
提出一种采用模拟乘法器和模拟积分器作为基本元件构成功率方向继电器的方案。
Based on Jiangsu social accounting matrix (SAM) decomposed multiplier analysis, this paper studies the relationship between economy and society of Jiangsu.
通过江苏社会核算矩阵(SAM)乘数分解，研究了江苏经济社会关联联系。
A converting circuit was proposed based on frequency-multiplier circuit for linear servo motor and PLC interface.
提出了一种基于倍频电路的直线伺服电机与PLC接口转换电路。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
Based on the characteristic of multi-path frequency selective channel, the algorithm combines rapid table lookup and Lagrange-multiplier method to iteratively search the optimal bit allocation scheme.
算法根据多径信道选择性衰落的特性，结合查表法和拉格朗日乘子的混合迭代搜索法，最优地分配各个子载波的传输比特数。
The described multiplier is based on the variable transconductance principle.
本文叙述一种可变跨导脉冲乘法器。
The 3D distribution of electric field in GEM (Gas Electron Multiplier) electrode is calculated based on the finite element method.
基于有限元方法对GEM电极的电场分布进行模拟和计算，得到了完整的三维电场分布。
Based on national Social Accounting Matrix (SAM), this paper studies the influence of electricity prices on national economy by multiplier analysis, and takes a quantitative analysis.
基于全国社会核算矩阵(sAM)，利用乘数分析方法研究电价的变化对国民经济的影响，并将影响结果进行量化。
The two basic component of rate-distortion model based on Lagrange multiplier in video coding are distortion and rate.
视频通信中的基于拉格朗日乘子法的率失真模型的两个基本组成部分是失真度和比特率。
The presentation of the finite field elements in WDB is studied. And based on the computing method for the optimum WDB, the design for the bit parallel multiplier of finite field is presented.
研究了有限域元素在弱对偶基（WDB）下的表示，基于弱对偶基下的最优弱对偶基的计算方法，给出了有限域比特并行乘法器的设计；
This paper presents a realization scheme based on shifting and adding operation, sub-expression, and multiplier module.
该文提出的无乘法器结构的滤波器实现方法主要基于移位相加操作、子表达式和乘法器模块的思想。
The novel multiplier structure is designed based on the basic computation format.
基于该运算形式，设计出新颖的乘法器架构。
The existing scheme use same Lagrange multiplier for each layers in LARDO-based SVC encoding.
在以往的方法中，不同的编码层使用相同的拉格朗日乘子。
The existing scheme use same Lagrange multiplier for each layers in LARDO-based SVC encoding.
在以往的方法中，不同的编码层使用相同的拉格朗日乘子。
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