Whereas the designed tag is readable and writable, E2PROM is adopted as the memory unit.
鉴于所设计的标签是可读写的，采用了E2PROM作为存储单元。
A memory unit in which instructions or data are permanently stored for use by the computer.
含有由计算机永久存储着的指令或数据的存储器。
The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.
其中包括地址缓冲、译码器、存储单元、灵敏放大器和输出缓冲电路。
In a microcomputer with a microprogrammed instruction set, it contains an additional control-memory unit.
在具有微程序控制的指令集的微型计算机中，它包含另外的控制存储单元。
The invention further provides an integrated preparation method for the memory unit in the copper interconnection process.
本发明还进一步提供了上述存储单元在铜互连工艺中的集成制备方法。
The memory unit mechanism is proposed to strengthen the local search ability of the algorithm and its calculation speed has been improved.
并采用记忆单元机制，增强了算法局部搜索的能力，提高了其计算速度；
A portion of the buffer cycle in which the logic or arithmetic unit must cease operation or neither will be able to communicate with the memory unit.
缓冲存储器周期的一部分，在这期间，逻辑与算术运算器必须中止操作或不能与存储器传输信息。
Decoder is one of the most important components in a memory unit, and its improvement can greatly diminish the access time of both register file and SRAM.
译码器是存储部件关键路径的重要组成部分，提高译码速度能有效提高寄存器文件和SRAM的读写速度。
The invention discloses a multi-resistance state resistor random-access memory unit and a preparation method thereof, and belongs to the technical field of microelectronics.
本发明公开了一种多阻态电阻随机存储器单元及其制备方法，属于微电子技术领域。
Further, when the management unit (103) receives an abnormal value trigger, the management unit sequentially stores data output from the measurement unit (101) at a main memory unit (104).
另外，如果管理器103接收到异常值触发，则管理器103顺序将从测量器101输出的数据存储在主存储器104中。
Further, when the management unit (103) receives an abnormal value trigger, the management unit sequentially stores data output from the measurement unit (101) at a main memory unit (104).
另外，如果管理器103接收到异常值触发，则管理器103顺序将从测量器101输出的数据存储在主存储器104中。
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