NROM memory cell, memory array, related devices and methods.
NROM存储器元件，存储器阵列，相关装置和方法。
The memory cell keeps better antibodies of the antibody population.
记忆单元保存抗体群中亲和力较高的抗体。
The invention discloses a memory cell array arranged multiple in rows and lines.
本发明公开了存储器单元阵列，以多行与多列排列。
The refresh portion reads and rewrites data from and in the memory cell in a power-down state.
而且，更新部在电源下降时对存储器单元进行读出及重新写入。
The invention is directed to a resistive memory cell on a substrate and a resistive memory array.
本发明公开了一种位于基底上的电阻式存储器单元和电阻式存储器阵列。
The invention reduces the size of the memory cell and ensures normal operation of the memory cell.
本发明能缩小存储单元的尺寸，并且保证存储单元能正常工作。
AIRS results in the memory cell pool after it is trained and classifies the original antigens by KNN.
AIRS通过训练产生记忆细胞池，利用最近邻原理对原始抗原分类。
The invention provides a memory cell transistor having multi-layer tunnel insulator and memory device.
本发明提供一种具有多层隧道绝缘体的存储器单元晶体管及存储器器件。
A two-port SRAM memory cell (20) includes a pair of cross-coupled inverters (40) coupled to storage nodes.
一种二端口SRAM存储器单元(20)包括耦合到存储节点的一对交叉耦合的反相器(40)。
The invention makes single memory cell possible to store multiple bits and increase memory capacity of cell.
故能在单一存储单元储存多个位，而可提高存储单元的存储容量。
This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell.
该存储器备有：非易失性的存储器单元和对存储器单元进行重新写入用的更新部。
Such integrated circuit includes a memory cell with a diode and an antifuse in communication with the diode.
所述集成电路包括具有二极管及与所述二极管连通的反熔丝的存储器单元。
The generation mechanism of stress induced leakage current (SILC) in flash memory cell is studied by experiments.
通过实验研究了闪速存储器存储单元中应力诱生漏电流(ILC)产生机理。
The advantage thereof is to reduce size of the memory cell, reduce programming interference, with paged erasing function.
本发明的优点在于减少存储器单元的大小、减低编程扰动、以及按页擦除的能力。
Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-d monolithic memory device.
类似地形成导电轨和存储单元二极管的附加层级，从而构建3- D单片存储装置。
A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained.
由此，可以得到能够抑制由积累的干扰而导 致的存储器单元的数据消失的存储器。
A computer memory cell ordinarily stores either a zero or a one, but a newly demonstrated example could also store a two or a three.
通常计算机的存储单元能存储0或1，但是一项新的研究证明了能够存储2或3。
A fast access time is achieved by using six-transistor CMOS memory cell, latched sense amplifier, and high-speed decoder circuit.
存储器采用六管CMOS存储单元、锁存器型敏感放大器和高速译码电路，以期达到最快的存取时间。
One of the main difficulties of quantum computation is that decoherence destroys the information in a quantum computer memory cell.
量子计算机存储单元的相干脱散，破坏量子态中的信息，是量子计算机难以实现的主要原因之一。
What sequence of events do you think would be required to move the contents of one memory cell in a computer to another memory cell?
你认为要搬移某记忆体单元的内容至另一记忆体单元需要哪些一连串的事件来完成？
A memory cell and a data line are controlled with a reset signal, so that data can be reliably outputted in the semiconductor device.
存储单元和数据线用复位信号来控制，以使数据可在该半导体器件中被可靠地输出。
In a sense, a memory cell containing an address can be thought of as pointing to another memory cell. Such cells are called Pointers.
在某种意义上，一个内存单元中存储的地址可以认为是指向另一个内存单元，这样的单元称为指针。
The present invention can fully cope with scale-down and high-integration by constituting a selectable memory cell substantially of one device.
借助于构 成基本上一种器件的可选择的存储单元，本发明完全适应按比例缩小和高密度集成。
In this algorithm, the data set to be analyzed is taken as the invading antigen and the memory cell generated ACTS as the initial cluster center.
算法中，待分析的数据被视为入侵性抗原，产生的记忆细胞作为聚类分析的初始中心。
The resistive memory cell comprises a first gate, a second gate, a common doped region, a contact plug, a bit line and a resistive memory element.
所述电阻式存储器单元包括第一栅极、第二栅极、共用掺杂区域、接触窗插塞、位线以及电阻式存储器元件。
A programmed region, i. e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed.
在编程此反熔丝一次可编程非易失存储器单元后，已编程的区域(例如为连结)可作为二极管，其形成于反熔丝上。
The second selection circuit connects the first bit line to the source side sensing circuit so that a source current of the first memory cell is sensed.
以及一第二选择电路，用于该读取操作模式，连接该第一位线至该源极端感测电路以感测该第一存储单元的源极电流。
The second selection circuit connects the first bit line to the source side sensing circuit so that a source current of the first memory cell is sensed.
以及一第二选择电路，用于该读取操作模式，连接该第一位线至该源极端感测电路以感测该第一存储单元的源极电流。
应用推荐