The resistive memory cell comprises a first gate, a second gate, a common doped region, a contact plug, a bit line and a resistive memory element.
所述电阻式存储器单元包括第一栅极、第二栅极、共用掺杂区域、接触窗插塞、位线以及电阻式存储器元件。
The reset state of a bit line is canceled when selected and connected to a read circuit for read, and information stored in a selected memory cell is read via the selected bit line.
当选择并且连接到用来读取的读取电路时，取消位线的复位状态并且通过所选的位线读取存储在所选存储器单元中的信息。
To reduce bit cost in the same generation of process, multi-bit in one cell technology has been developed for flash memory.
为了在现有条件下进一步降低闪速存储器的单位成本，已开发了各种单管多位技术。
The second selection circuit connects the first bit line to the source side sensing circuit so that a source current of the first memory cell is sensed.
以及一第二选择电路，用于该读取操作模式，连接该第一位线至该源极端感测电路以感测该第一存储单元的源极电流。
The second selection circuit connects the first bit line to the source side sensing circuit so that a source current of the first memory cell is sensed.
以及一第二选择电路，用于该读取操作模式，连接该第一位线至该源极端感测电路以感测该第一存储单元的源极电流。
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