Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.
因此研究系统总线协议及其实现技术对于隐藏访存延迟和提高访存速度具有重要意义。
The access rate of the memory is determined by crucial path which is between data input and data output.
静态存储器的存取速度由地址输入到数据输出的关键路径决定。
The access rate of the memory is determined by crucial path which is between data input and data output.
静态存储器的存取速度由地址输入到数据输出的关键路径决定。
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