Software pipelining has been combined with several memory optimization technologies for higher performance by hiding memory access latency.
为了减轻存储系统影响，软件流水结合了一些存储优化技术，通过隐藏存储延迟来提高性能。
The tightly-coupled nature of the CMP allows very short physical distances between processors and memory and, therefore, minimal memory access latency and higher performance.
CMP紧密耦合的本质使处理器与内存之间的物理距离很短，因此可提供最小的内存访问延迟和更高的性能。
This increases the latency of the task's memory access until its data is in the cache of the new CPU.
这就增加了任务的内存访问延迟，这些时间用来将其数据移入新cpu的内存中。
For example, each processor has its own memory but also access to Shared memory with a different access latency.
例如，每个处理器拥有自己的内存，访问共享内存时具有不同的访问延迟。
Memory and CPU based access can provide much lower latency and greater throughput than disk and network based access.
相比基于磁盘和网络的访问，基于内存和CPU的访问能提供更低的延迟和更高的吞吐量。
To to minimize access latency, and thus improve performance, it's best to have your data in the closest memory.
为了尽可能减少访问延时并由此提高性能，最好把数据放在最近的内存中。
Each processor has equal access to the Shared memory (the same access latency to the memory space).
每个处理器可同等地访问共享内存(具有相同的内存空间访问延迟)。
Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.
因此研究系统总线协议及其实现技术对于隐藏访存延迟和提高访存速度具有重要意义。
Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.
因此研究系统总线协议及其实现技术对于隐藏访存延迟和提高访存速度具有重要意义。
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