We put forward a technology named fixed instruction multiple data in order to accelerate the loop, and design a chip-multiprocessors architecture.
为加速循环程序执行，提出了固定指令多数据流计算模型，并设计了一个单芯片阵列处理器体系结构。
According to the characteristics of digital processing applications, loop buffering can be used to reduce the power consumption of instruction memories while fetching instructions.
但是，根据数字信号应用的特点，可以采用循环缓冲来减小指令存储器的功耗。
On modern processors, where a HLT (halt) instruction saves significant amounts of power and heat, the idle task almost always consists of a loop which repeatedly executes HLTinstructions.
在现代的处理器中，HLT停机指令节省了大量的电能与执量，空闲任务几乎总是由一个重复执行HLT停机指令的循环组成。
Software pipelining is a loop scheduling technique which extracts instruction level parallelism by overlapping the execution of several consecutive iterations.
软件流水是一种开发循环程序指令级并行性的技术，它通过并行执行连续的多个迭代来加快循环的执行速度。
Software pipelining is a loop scheduling technique which extracts instruction level parallelism by overlapping the execution of several consecutive iterations.
软件流水是一种开发循环程序指令级并行性的技术，它通过并行执行连续的多个迭代来加快循环的执行速度。
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