Loop filter: the encoder attempts to optimize the loop filter parameters for maximum PSNR.
回放过滤器：编码器试图优化回放过滤器的参数，以达到最大的峰值信噪比。
The method of designing the loop filter with the phase margin and loop bandwidth is displayed.
并提出了从环路带宽和相位余量出发设计环路滤波器的方法。
In this article, PLL theory, design of loop filter and phase noise theory are introduced at first.
本文先介绍了锁相环的工作原理，环路滤波器的设计并对相位噪声的理论进行了阐述。
Then introduced the entropy decoding and adaptive in-loop filter which are time-consuming modules.
接着对解码中比较耗时的熵解码及自适应环路滤波模块做了详细的介绍。
This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter.
本文讨论的全数字锁相环包括过零检测器和环路滤波器。
When the PFD does not generate pulses in lock mode, the charge pump does not provide charge to the loop filter.
当PFD在锁定模式中不生成脉冲时，电荷泵不提供电荷给环路滤波器。
The timing error detector and loop filter of HDPLL are all digitized, whereas the VCXO employs analog components.
HDPLL中定时误差检测器、环路滤波器是全数字的，而VCXO使用了模拟器件。
The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。
Noise which comes from both active and passive circuit element in loop filter will deteriorate phase noise of output signal.
环路滤波器中的有源和无源器件均有噪声产生，此类噪声会叠加在输出信号上，从而恶化输出信号的相位噪声。
A passive loop filter scheme and the design method of the filter for current charge pump PLL frequency synthesizer chip are given in the paper.
针对电流型电荷泵PLL频率综合器芯片，提出一种称为极值相位裕量的无源环路滤波器方案和设计方法。
The narrower the loop filter bandwidth the smaller the achievable phase error. This comes at the expense of slower response and reduced capture range.
滤波器的带宽越窄，得到的相位差越小，其代价为响应变慢俘获范围变小。
Then analyses the complexity of AVS decoder and finds out the the critical modules are motion compensation, integer transform, quantization and loop filter.
然后对解码器进行复杂度分析，找出解码耗时的关键部分分别为运动补偿、反变换、环路滤波等模块。
The function of a loop filter is to filter high-frequency signal out of the output voltage from PFD and CP, thus the output signal from VCO will be purified.
环路滤波器的作用就是滤除从PFD&CP出来的电压中的高频成分，从而纯化VCO的输出信号。
The loop filter is run after decoding or encoding a frame and serves to perform extra processing on a frame, usually to remove blockiness in DCT-based video formats.
回放过滤器在解码或编码一个帧后运行，在帧上执行一些额外的处理，在基于DCT的格式中通常是消除区块效应。
Upon the low power design consideration, a hybrid active-passive loop filter is employed and the signal summing block is removed by using discrete-time differentiation technique.
基于低功耗设计考虑，调制器采用有源-无源混合型环路滤波器，并通过离散时间微分技术移除信号求和模块。
According to transfer functions of the loop filter and the single phase locked loop system, it figures out the loop filters parameters, and introduces the selection of loop bandwidth.
根据环路滤波器传递函数以及单环锁相系统的传递函数，计算出环路滤波器的各个参数，并介绍了环路带宽的选择。
The paper analyzes the design method of passive loop filter thoroughly, and presents a effective design method. The method has obvious advantage comparing to the design method in existence.
对锁相环的环路滤波器的设计方法进行了深入研究，给出了一种环路滤波器设计方法，该设计方法与现有设计方法相比具有较明显的优点。
This paper gives the design and experimental results of low noise NPLL frequency synthesizer and concludes that the passive loop filter is more suitable for low noise design than active loop filter.
介绍低相噪NPLL频率综合器的设计及实验结果。提出用无源环路滤波器比用有源环路滤波器更好，可获得低相噪设计。
On condition that the open-loop parameters are given, the loop filter of feedback seismometer with a velocity transducer is one of the key factors of effecting seismometer main technical performances.
在开环参数一定的条件下，速度传感反馈地震计中的环路滤波是影响地震计主要技术指标的关键环节之一。
This paper develops a hardware architecture of the multi-standard loop-filter that can be used for both standards in various codec systems.
本文的工作就是设计一种支持这两种标准编解码的环路滤波器硬件架构，并对其进行验证和性能分析。
This paper develops a hardware architecture of the multi-standard loop-filter that can be used for both standards in various codec systems.
本文的工作就是设计一种支持这两种标准编解码的环路滤波器硬件架构，并对其进行验证和性能分析。
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