Because of the fading characteristic in troposcatter channel, the mechanism of traditional phase locked loop is difficult to achieve the effect in troposcatter communication.
由于对流层散射信道存在严重的衰落现象，故而传统的锁相环机制在散射通信中往往难以奏效。
Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).
本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。
The controller make up of TMS320F2812 DSP chip, detecting circuits include sampling circuit, modulate circuit and phase locked loop and other periphery control and drive circuit.
本文设计的控制器以TMS320F2812DSP芯片为核心，加上检测电路（包括采样电路、调理电路、锁相环等）和其它外围控制和驱动电路构成。
Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).
然后介绍了锁相环(PLL)的基本结构、相位模型、频率响应、噪声及杂散性能。
Slip correlative taking and delay locked loop are used for the synchronization, taking, locking of PN code.
采用滑动相关捕获和延迟锁定环实现伪码的同步、捕获和跟踪；
According to transfer functions of the loop filter and the single phase locked loop system, it figures out the loop filters parameters, and introduces the selection of loop bandwidth.
根据环路滤波器传递函数以及单环锁相系统的传递函数，计算出环路滤波器的各个参数，并介绍了环路带宽的选择。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
本文分析了数字锁相环路的寄生频偏，它是现代通讯系统中频率合成器的重要指标之一。
An automatic accurate synchronization control scheme which adopts phase locked loop principle is presented.
利用锁相环路原理提出锁相自动准同期控制方案。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
The possibility of using this kind of phase-locked loop under noise interference and the problems of filter design are discussed.
文中还讨论了在噪声作用下采用这种环路的可能性和滤波器的设计问题。
Introduces the basic principle of phase-locked loop and NE564 PLL circuit structure and properties, and the use of phase-locked NE564 demodulating circuit and phase-locked frequency circuit.
介绍了锁相环的基本原理和锁相环ne564的电路结构和性能，及其用ne564构成的锁相解调电路和锁相倍频电路。
To this end the current multipath estimation delay locked loop(MEDLL) was investigated and improvements were proposed based on the zero-point fixed principle.
为了消除扩频系统中的多径干扰，文章基于稳态零点不变的原则对多径估计延迟锁相环（MEDLL）进行研究及改进。
The simulation results prove that the three-phase phase-locked loop can work well in disturbance situation and variable frequency system when the frequency of the inputs is variable.
并对相位突变和频率突变的情况进行了仿真研究，说明在相位和频率发生变动时三相锁相环仍能有效地锁定相位，能够满足系统变频的要求。
This article presents a new design structure of variable bandwidth phase-locked loop based on improving phase-locked loop of actively mode-locked fiber laser.
对主动锁模光纤激光器的锁相环进行改进，提出一种新型的“变带宽锁相环”的设计结构。
According to the theory of phase-locked loop, we use reflected photoelectric sensor to carry out the color recognition.
根据锁相环的原理，使用反射式光电传感器实现了系统的颜色识别。
A fast all digital phase-locked loop with automatic modulus control is presented.
提出了一种具有自动变模控制的快速全数字锁相环。
This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS), a method to improve the precision of DDS and reduce its phase truncation error is also given.
介绍了锁相环(PLL)技术和直接数字式频率合成(DDS)技术的基本工作原理，给出了一种提高DDS输出频率精度及减小其相位截断误差的方法。
In the process of signal digital intermediate-frequency received, digital down convertion, frequency tracking of carrier and phase locked loop are the keys.
在信号的中频数字接收过程中，数字下变频、载波频率与相位跟踪是设计的关键所在。
The paper introduces a kind of clock recovery system based on phase-locked loop with bi-directly incident phase-comparator.
介绍了一类基于双向输入型鉴相器锁相环技术的时钟恢复系统。
The design and implementation of quadrature waveform generator are described based on the AT89C52, phase-locked loop(PLL) and switched-capacitor filter(SCF).
描述了基于AT89C52单片机、锁相环和开关电容滤波器的正交信号发生器的设计和实现方法。
Based on digital delay-locked loop, the mix signal technique is used to implement the digital delay locked loop with the resource control technique.
以数字延迟锁相环为基础，并采用数模混合技术，实现了带电源控制的数字延迟锁相环。
Phase locked loop technique offers a way to resolve this problem.
锁相式频率合成技术提供了解决这一问题的思路。
In this thesis the basic architecture and the performance evaluation of phase-locked loop are presented.
本文研究了锁相环的基本结构与系统构架及其性能优劣。
The software phase-locked loop (SPLL) technology in the steady speed control of permanent magnet brushless DC motor (BLDCM) in gyro was discussed.
研究了软件锁相环技术在陀螺用无位置传感器无刷直流电机稳速控制系统中的应用。
The paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.
本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案。
Furthermore, the working principle and phase noise of frequency-locked loop are analyzed and discussed in this paper.
给出了实验结果，并对锁频环的工作原理、相位噪声进行了分析和讨论。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
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