Fault simulation is reduced to logic simulation on the original circuit.
故障模拟被简化为在原始电路上的逻辑模拟。
With the rapid growth of complexity of VLSI, more and more logic simulation has adopted parallel discrete event simulation.
随着大规模集成电路的复杂性日益增加，逻辑模拟开始采用并行离散事件模拟技术。
Waveforms are used as a tool for describing circuits during logic simulation and accurate simulation is achieved by computing and checking waveforms.
在逻辑模拟中用波形作为电路状态的描述工具，通过对波形的计算和检查实现精确的模拟。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
This method is based on multi-delay modeling, SPICE and logic simulation. It provides an effective tool to design and analysis asynchronous data-path.
这种方法在进行性能分析时基于多延迟模型、SPICE和逻辑仿真，可以作为异步数据通路设计和分析的一种有效工具。
This method is based on multi-delay modeling, SPICE and logic simulation. It provides an effective tool to design and analysis asynchronous data-path.
这种方法在进行性能分析时基于多延迟模型、SPICE和逻辑仿真，可以作为异步数据通路设计和分析的一种有效工具。
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