• The circuits used are Chua 'circuit and phase lock loop.

    所用的电路为蔡氏电路和锁相环电路。

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  • In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.

    该方案利用信号自身的特性,采用数字逻辑设计,有效避免了性能不高的锁相环的使用。

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  • The electronic design is similar to the one for crystal oscillator lock loop but the parameters are different.

    腔自动调谐的电路设计和晶体振荡器伺服环路类似,仅仅环路参数不同。

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  • Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.

    基于模糊逻辑控制的数字锁相环,用于通信系统中的载波恢复。

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  • Phase lock loop and benchmark resistance compensating technologies were used to improve the detection precision, the error was less than 10%.

    通过锁相放大技术及基准电阻补偿方法提高了测量的精度,误差在10%以内。

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  • The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.

    环路为反馈结构,包括插值器、时钟误差检测和环路滤波器三个部分。

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  • The orthogonal analog phase lock loop is used to get the timing information of the impulse radio system and the multi-path component separation.

    使用正交模拟锁相环路对无载波的脉冲无线电系统实现多径捕获和同步提取。

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  • The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.

    对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。

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  • The phase lock loop is a feedback control system that makes two telecommunication signals' phase synchronization, suitable to the synchronous trigger circuit of the convertor device.

    锁相环路是完成两个电信号相位同步的反馈控制系统,适宜于变流装置的同步触发电路之中。

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  • The performance of synchronization tracking using pilot is analyzed, followed by a numerical method to determine the optimal lock loop parameters to minimize average bit error rate (BER).

    分析了利用导频同步跟踪的性能,以及提出了一个数值方法确定最优环路参数以最小化误码率。

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  • Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking.

    由于有锁频环的频率牵引,锁相环路滤波器可以设计得很窄,具有很好的抑噪性能,满足精确跟踪载波相位的要求。

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  • The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.

    数字锁相环路(DPLL)是数字相干解调技术的核心。

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  • We have mainly researched two FM signal demodulation techniques called Frequency Spectrum Separation and Phase Lock Loop in the first part.

    一次解调中研究了频谱分离法和锁相法两种实现鉴频的技术。

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  • We have mainly researched two FM signal demodulation techniques called Frequency Spectrum Separation and Phase Lock Loop in the first part.

    一次解调中研究了频谱分离法和锁相法两种实现鉴频的技术。

    youdao

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