Then it mainly discusses the hardware design of the key unit in LDPC decoder-check functional unit.
紧接着讨论了LDPC译码器中的核心运算单元一校验功能单元的硬件设计。
For the detected error words by the LDPC decoder, the characteristics of code bits reliability information is investigated.
分析了低密度校验(LDPC)码译码所产生的错误码字中码位的译码输出量可靠度信息的统计特性。
With the development of LDPC algorithm which has a hardware-friendly trend, the VLSI realization of LDPC decoder is becoming ever the focus of researchers.
随着LDPC译码算法领域的研究日趋成熟和越来越易于硬件实现的发展趋势，LDPC译码器的VLSI实现才逐渐成为研究者关注的焦点。
At present, more and more communication system use LDPC code as the channel coding scheme, the architecture in this paper will give a reference to design and implementation of other LDPC decoder.
目前越来越多的通信系统采用LDPC码作为纠错码，这种硬件结构对其它系统的LDPC译码器设计及实现有一定的借鉴意义。
Advanced researches on decoding algorithm and decoder structure of QC LDPC code are the focus of this thesis.
本论文主要对准循环ldpc码的译码算法和译码器结构进行了较深入的研究。
Moreover, this decoder is also compatible with various block-lengths and code-rates, so only one decoder is needed for different LDPC codes with the same column weight.
该译码器可兼容多种码长、多种码率的LDPC码，因此只需要设计一个译码器，就可以完成对具有相同列重的不同LDPC码的译码。
Based on the structure of quasi-cyclic LDPC codes, a synchro partially parallel decoder is proposed in this paper.
该文根据准循环ldpc码的结构特点，提出了一种同步部分并行结构的译码器。
The decoder employs the Normalized MSA algorithm, and Partially Parallel structure for LDPC code in CMMB standard.
本译码器采用改进的最小和译码算法及符合CMMB标准要求的部分并行译码器结构。
The decoder employs the Normalized MSA algorithm, and Partially Parallel structure for LDPC code in CMMB standard.
本译码器采用改进的最小和译码算法及符合CMMB标准要求的部分并行译码器结构。
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