VLSI layout circuit extraction provides a reliable tool for the estimation of circuit's performance.
集成电路版图提取为精确估计电路性能提供了可靠的手段。
A new hierarchical approach for layout circuit extraction was presented to increase its efficiency.
为提高版图电路提取效率，提出了一种新的层次式版图电路提取方法。
A new hierarchical approach for layout circuit extraction was presented to increase its efficiency.
为提高版图电路提取效率，提出了一种新的层次式版图电路提取方法。
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