The difficulty of RS encoder IP core design is how to improve operation rate of encoding circuit.
RS编码器IP核设计的难点是提高编码电路的编码运算速度。
The compressor has been used in the IP software core design of 32bits floating multiplier as a module, and acquire a good result.
此压缩器已作为一个压缩模块，用在32位浮点乘法器的软核设计中，得到了很好的结果。
This thesis introduces the design of USB2.0 IP CORE for USB device controller, and mainly about the design of the main controller of the IP CORE.
本文介绍一种USB2.0设备控制芯片IP核的设计，并且主要对其中的主控制器的设计进行介绍。
This paper introduces MD5 algorithm, then gives the whole framework and schemes of design and implementation of important modules in IP-CORE.
文章介绍了MD5算法，给出了IP核的整体架构及其重要模块的设计实现方案。
Reusable design method of IP core is the main method in designing large scale integrated circuits.
IP核可重用设计方法是未来大规模集成电路的主流设计方法。
This paper discusses the design of hard and soft IP core of cycling shifter particularly on basement of analyzing the arithmetic and capability of cycling shift operation.
文章在进行循环移位运算的算法和性能分析的基础上，对循环移位器IP软核与硬核的设计作了详细阐述。
Focused on the hardware design of the fibre channel link layer, this paper applied modularization thinking in the top-down design process, with relevant IP core interfaces.
以模块化的方式采用自顶向下的设计思路，重点阐述了光纤通道链路层的硬件设计方法，并给出了IP核的相关接口。
The reuse of multimedia processor IP core is the key and difficulty of programmable media SOC design.
媒体处理器IP核重用成为可编程媒体系统芯片设计的重点和难点。
This paper presents an efficient design of AES algorithm's IP core in FPGA using pipelining technique and optimized methods.
文章基于FPGA采用流水线技术和优化设计，提出了一种更高效的AES算法IP核的设计方法。
The approach of the IP-Core design and IP-Core interconnection in the integrated system are discussed with the example of the Chip PCI-A429 developed by CARERI in this paper.
以自行研制的PCI-A429芯片为例，讨论了内核设计以及系统集成中内核互连的问题。
The paper studies the design of data paths and the communication mechanism of control information, focusing on the reuse of media processor IP core in media SOC.
本文围绕媒体处理器IP核在媒体系统芯片中的重用，对数据通路设计及控制信息通信机制进行研究。
Design flow has to take the advantage of mature and proven IPs (IP reuse) will allow designers to make easier upgrade in the core key technologies to differentiate themselves.
设计流程必须利用成熟且经过验证的IP (IP复用)，令设计者更容易的升级他们的核心关键技术，使他们的设计具有与众不同的优势和特点。
Preorder module IP core is widely used in the design of System on chip (SOC), IP core is becoming the kernel component in the designing of future chip.
系统级芯片(SOC)的设计大多采用以ip核为主的预定制模块，IP核已经成为未来主流芯片设计的核心构件。
The parameterized design about the C8051 micro controller IP soft core is studied.
研究了C8051微控制器IP软核的参数化设计。
The dial plan is at the very core of any telephony implementation and as such, is one of the most important and complex elements in IP telephony design.
拨号计划是任何电话实施方案的非常核心的部分，也是IP电话设计中最重要最复杂的部分。
This paper introduces the data encryption standard algorithm briefly, and discusses an IP-CORE design and the FPGA implementation of the algorithm.
该文介绍了数据加密标准算法，讨论了该算法的一种IP核设计及其FPGA实现。
According to the requirement of the VLSI and the wide application of power electronics, IP soft core of SPWM generation system is designed. And it can be widely applied in system level chip design.
论文针对目前大规模集成电路设计要求，结合电力电子应用，设计了一个SPWM信号产生系统IP软核，该软核可广泛应用于系统级芯片设计中。
According to the design reuse methodology, this dissertation focus on the research of widely used 80c51 IP soft core, including the test and application technology.
本文基于可复用设计方法学，对用途广泛的微处理器80c51IP软核的测试方法和应用技术进行研究。
Finally, the dissertation research on the application technology of 80c51 IP soft core, and design an IP-base system used for high speed data collection.
最后，研究IP软核应用技术，设计基于80c51 IP软核的高速数据采集应用系统。
How to choose an appropriate method of IP core verification has been the primary issue for many chip design corporations.
选择一种合适的验证技术对于很多芯片设计公司而言已经成为了首要问题。
As a kind of IP core, IP soft core has a big advantage in reuse design because of its flexibility.
作为IP核形式之一的IP软核，灵活性高，在IP核复用中有很大优势。
The design of is (Integrated system) is executed on the basis of IP core, with HDL as the main method of systematic function description and by virtue of EDA tools on the computer platform.
集成系统(IS)设计以IP核为基础，以硬件描述语言为系统功能的主要描述手段，借助于以计算机为平台的EDA工具来进行。
And finally, simulation results and verification by hardware test in FPGA show that the design of the IP core is valid and the proposed optimization strategy to reduce the memory is effective.
对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明，文章提出的优化方案可行、有效，极大地降低了硬件资源占用和功耗。
Finally completed the IP soft core testing, and shows the correct of the design of YAK SOC interface IP soft core.
最后完成了IP软核验证，结果表明了本文所设计的YAKSOC接口IP软核设计的正确性。
The Design and Implementation of Core Serving Control Function Entity in the IP Multimedia System;
过去的核心业务系统通过分开的应用程序提供了相同的功能。
The Design and Implementation of Core Serving Control Function Entity in the IP Multimedia System;
过去的核心业务系统通过分开的应用程序提供了相同的功能。
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