A novel IP core for Flat Panel Displays (FPD) driver has been designed.
介绍了一种全新的平板显示器件通用驱动电路IP核的总体设计。
The IP core contains a Successive Approximation ADC and interface control circuit.
该IP核由逐次逼近型模数转换器以及控制接口电路所构成。
The structure of IP core and the hardware implementation of convolution were investigated.
对IP核所采用的结构、卷积运算的硬件实现进行研究。
The difficulty of RS encoder IP core design is how to improve operation rate of encoding circuit.
RS编码器IP核设计的难点是提高编码电路的编码运算速度。
Reusable design method of IP core is the main method in designing large scale integrated circuits.
IP核可重用设计方法是未来大规模集成电路的主流设计方法。
As a kind of IP core, IP soft core has a big advantage in reuse design because of its flexibility.
作为IP核形式之一的IP软核，灵活性高，在IP核复用中有很大优势。
The reuse of multimedia processor IP core is the key and difficulty of programmable media SOC design.
媒体处理器IP核重用成为可编程媒体系统芯片设计的重点和难点。
MPLS is an IP core technology of the next generation. Currently it is actively driven to worldwide deployment.
MPLS技术是新一代的IP骨干网络技术，目前正在大规模的推广使用中。
The IP core offers more meaning to system on single chip (SOC) in wireless sensor networks address adjustment.
为无线传感器网络节点单芯片系统的地址重构集成化提供了意义。
The IP core has the function of detecting smart card, managing power, resetting, controlling reading and writing etc.
该IP核能实现对智能卡的探测、电源管理、复位和读写控制等功能。
How to choose an appropriate method of IP core verification has been the primary issue for many chip design corporations.
选择一种合适的验证技术对于很多芯片设计公司而言已经成为了首要问题。
This paper presents an efficient design of AES algorithm's IP core in FPGA using pipelining technique and optimized methods.
文章基于FPGA采用流水线技术和优化设计，提出了一种更高效的AES算法IP核的设计方法。
The simulation software conducts the power analysis of cryptographic algorithm IP core which is described by hardware language.
该软件完成对硬件描述语言实现的密码算法IP核进行功耗分析。
A sort of reconfiguration cycling shifter for Block Cipher Algorithm, which was designed as IP core for reusing, was studied in this paper.
文章对一种适用于分组密码算法的循环移位器ip核的设计进行了研究，该IP核的可重构设计使其具有可复用性。
Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.
另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试(BIST)。
This thesis introduces the design of USB2.0 IP CORE for USB device controller, and mainly about the design of the main controller of the IP CORE.
本文介绍一种USB2.0设备控制芯片IP核的设计，并且主要对其中的主控制器的设计进行介绍。
This paper introduces the concept of all IP core network, then discusses the evolution of wireless network, backbone network, signalling network.
本文介绍了全IP核心网的概念以及无线网、骨干网、信令网的演进。
An intrinsic accuracy, adjustable resolution ramp generator IP core designed for the column single-slope ADC in a CMOS image sensor is presented.
基于CMOS图像传感器应用，针对列并行的单斜模数转换器设计了一种内在精度高、分辨率可调的斜坡发生器ip核。
Preorder module IP core is widely used in the design of System on chip (SOC), IP core is becoming the kernel component in the designing of future chip.
系统级芯片(SOC)的设计大多采用以ip核为主的预定制模块，IP核已经成为未来主流芯片设计的核心构件。
The algorithms for controlling the system and the filter algorithm are designed into the IP core to increase the capacity of computing and running of system.
通过控制算法和复杂的滤波算法设计成IP核，进行软件程序的固化，提高了计量系统的计算、运行能力。
MPLS is a key technique which can solve problems existed in IP core network such as the performance of forwarding, differ service, traffic engineer and so on.
MPLS是一项有效解决核心网络转发性能、区分服务、流量工程等问题的关键技术；
The paper studies the design of data paths and the communication mechanism of control information, focusing on the reuse of media processor IP core in media SOC.
本文围绕媒体处理器IP核在媒体系统芯片中的重用，对数据通路设计及控制信息通信机制进行研究。
Experiments show that this testing frame can make an effective test on IP cores and take SOC environment of IP core into account while keeping high code coverage.
通过实验验证，该测试方法能够在保证一定代码覆盖率的前提下，对IP核进行有效的测试，并提高了测试后IP核的可移植性。
Having been applied in practical project, the result indicates that the IP core is reliable, powerfully extensible. It has satisfied technical target of real system.
通过实践表明，本文设计的时钟采样帧发生器IP核可靠易用，可扩展功能强，满足了实际应用系统的技术要求。
This paper discusses the design of hard and soft IP core of cycling shifter particularly on basement of analyzing the arithmetic and capability of cycling shift operation.
文章在进行循环移位运算的算法和性能分析的基础上，对循环移位器IP软核与硬核的设计作了详细阐述。
Focused on the hardware design of the fibre channel link layer, this paper applied modularization thinking in the top-down design process, with relevant IP core interfaces.
以模块化的方式采用自顶向下的设计思路，重点阐述了光纤通道链路层的硬件设计方法，并给出了IP核的相关接口。
IP core web management system can organize and manage the data of IP cores effectively, and provide a convenient platform for users to search and choose the right IP cores.
IP核网络管理系统可以有效的组织和管理IP核数据，并且为用户查找、选择合适的IP核提供一个便利的公共平台。
According to the theory in video compression as well as the simulation and verification requirement in IP core designing, the FPGA based IP core simulation platform is developed.
结合视频压缩的理论以及IP核设计中对于仿真验证的要求，本文设计了视频压缩IP核FPGA仿真验证平台。
Based on the theory of modularization, the IP core of GPIB is divided into three modules: module for port function of GPIB, module for inner register and module for data transmission.
本设计采用模块化设计的思想，将GPIB接口IP核分成三个模块：GPIB接口功能模块、内部寄存器模块和数据传输控制模块。
Mercury's serial RapidIO IP core provides customers with proven, deployed interconnect technology that enables high performance and flexibility for a variety of communication applications.
Mercury公司的串行RapidIOIP内核为客户提供可靠互连技术，保障多种通信应用的高性能和灵活性。
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