Finally analyzes the interface signals of IP-CORE, and estimates its performance, gives estimating parameters.
最后分析了IP核的接口信号，并对IP核的性能进行了评估，给出了评估参数。
This paper introduces MD5 algorithm, then gives the whole framework and schemes of design and implementation of important modules in IP-CORE.
文章介绍了MD5算法，给出了IP核的整体架构及其重要模块的设计实现方案。
This paper introduces the data encryption standard algorithm briefly, and discusses an IP-CORE design and the FPGA implementation of the algorithm.
该文介绍了数据加密标准算法，讨论了该算法的一种IP核设计及其FPGA实现。
The approach of the IP-Core design and IP-Core interconnection in the integrated system are discussed with the example of the Chip PCI-A429 developed by CARERI in this paper.
以自行研制的PCI-A429芯片为例，讨论了内核设计以及系统集成中内核互连的问题。
Your organization may have an environmental policy, but has it filtered through to your core business or your IP Strategy?
你的组织也许有一个环境政策，但是它是否已经被筛选到了你的核心业务或者知识产权战略里了呢？
The services in the core may represent intellectual property (IP) critical to the business.
这些核心服务可能代表了企业核心的知识产权(IP)。
Recall that the Internet protocol (IP) is the core network layer protocol that sits below the transport protocol (most commonly the Transmission Control protocol, or TCP).
回想一下，InternetProtocol (IP)是传输协议(通常称为传输控制协议或TCP)下面的核心网络层协议。
Mercury's serial RapidIO IP core provides customers with proven, deployed interconnect technology that enables high performance and flexibility for a variety of communication applications.
Mercury公司的串行RapidIOIP内核为客户提供可靠互连技术，保障多种通信应用的高性能和灵活性。
MPLS is a key technique which can solve problems existed in IP core network such as the performance of forwarding, differ service, traffic engineer and so on.
MPLS是一项有效解决核心网络转发性能、区分服务、流量工程等问题的关键技术；
Add the following property to $HADOOP_HOME/conf/core-site.xml to set the NN IP/ port
把以下属性添加到 $HADOOP_HOME/conf/core-site.xml 中以设置NNIP/端口
The results show that, users can control a remote motor by sending commands in a WEB browser, and simply replacing the signal generation IP core, users can control different type of motors.
结果表明：用户能够通过浏览器发送命令，实现对电机的远程控制，并且通过替换硬件IP核，实现对不同类型电机的控制。
This paper introduces the concept of all IP core network, then discusses the evolution of wireless network, backbone network, signalling network.
本文介绍了全IP核心网的概念以及无线网、骨干网、信令网的演进。
Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.
另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试(BIST)。
The difficulty of RS encoder IP core design is how to improve operation rate of encoding circuit.
RS编码器IP核设计的难点是提高编码电路的编码运算速度。
The frame model of the next generation network comes into being which were based on IP core network and other applying being linked to the core by Access network.
而以IP核心网为骨干，其他应用通过接入网连接到核心成为下一代网路的基本架构模型。
This thesis introduces the design of USB2.0 IP CORE for USB device controller, and mainly about the design of the main controller of the IP CORE.
本文介绍一种USB2.0设备控制芯片IP核的设计，并且主要对其中的主控制器的设计进行介绍。
A novel IP core for Flat Panel Displays (FPD) driver has been designed.
介绍了一种全新的平板显示器件通用驱动电路IP核的总体设计。
Reusable design method of IP core is the main method in designing large scale integrated circuits.
IP核可重用设计方法是未来大规模集成电路的主流设计方法。
This paper discusses the design of hard and soft IP core of cycling shifter particularly on basement of analyzing the arithmetic and capability of cycling shift operation.
文章在进行循环移位运算的算法和性能分析的基础上，对循环移位器IP软核与硬核的设计作了详细阐述。
Experiments show that this testing frame can make an effective test on IP cores and take SOC environment of IP core into account while keeping high code coverage.
通过实验验证，该测试方法能够在保证一定代码覆盖率的前提下，对IP核进行有效的测试，并提高了测试后IP核的可移植性。
The paper studies the design of data paths and the communication mechanism of control information, focusing on the reuse of media processor IP core in media SOC.
本文围绕媒体处理器IP核在媒体系统芯片中的重用，对数据通路设计及控制信息通信机制进行研究。
The reuse of multimedia processor IP core is the key and difficulty of programmable media SOC design.
媒体处理器IP核重用成为可编程媒体系统芯片设计的重点和难点。
Preorder module IP core is widely used in the design of System on chip (SOC), IP core is becoming the kernel component in the designing of future chip.
系统级芯片(SOC)的设计大多采用以ip核为主的预定制模块，IP核已经成为未来主流芯片设计的核心构件。
This paper presents an efficient design of AES algorithm's IP core in FPGA using pipelining technique and optimized methods.
文章基于FPGA采用流水线技术和优化设计，提出了一种更高效的AES算法IP核的设计方法。
According to the theory in video compression as well as the simulation and verification requirement in IP core designing, the FPGA based IP core simulation platform is developed.
结合视频压缩的理论以及IP核设计中对于仿真验证的要求，本文设计了视频压缩IP核FPGA仿真验证平台。
Focused on the hardware design of the fibre channel link layer, this paper applied modularization thinking in the top-down design process, with relevant IP core interfaces.
以模块化的方式采用自顶向下的设计思路，重点阐述了光纤通道链路层的硬件设计方法，并给出了IP核的相关接口。
As a kind of IP core, IP soft core has a big advantage in reuse design because of its flexibility.
作为IP核形式之一的IP软核，灵活性高，在IP核复用中有很大优势。
An intrinsic accuracy, adjustable resolution ramp generator IP core designed for the column single-slope ADC in a CMOS image sensor is presented.
基于CMOS图像传感器应用，针对列并行的单斜模数转换器设计了一种内在精度高、分辨率可调的斜坡发生器ip核。
The IP core contains a Successive Approximation ADC and interface control circuit.
该IP核由逐次逼近型模数转换器以及控制接口电路所构成。
The IP core contains a Successive Approximation ADC and interface control circuit.
该IP核由逐次逼近型模数转换器以及控制接口电路所构成。
应用推荐