SCSI-1 defined an 8-bit parallel interface with a 5MHz data clock, providing a maximum data transfer rate of 5 megabytes per second (MB/s).
SCSI-1定义了一种具有5MHz数据时钟的8-bit并行接口，能提供最高 5 兆字节每秒（5MB/s）的数据传输速率。
The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟信号进行控制，从而为器件与微处理器或DSP轻松接口创造了条件。
It is helpful to the designer of serial interface communication program of the real time clock device.
该方法对于实时时钟器件串行接口通信程序的设计具有一定的借鉴作用。
Interface and download chip is control-oriented and has complex clock relationships, therefore timing design is the key and difficult point.
自启动预载接口芯片以控制为主，时钟关系复杂。时序设计是整个设计的重点和难点。
The serial interface operates in internal clocking (master) mode, the AD7721 providing the serial clock.
串行接口在内部时钟(主)模式下工作，AD 7721提供所需的串行时钟。
Through the software the practical watching clock for interface module of GPS is implemented and the dependence on the PPS pulse is reduced.
GPS接口板通过软件方式实现实用化的守时钟，降低对单个PPS秒脉冲的依赖性。
The hardware of the monitoring system mainly consists of the DSP controller, nonvolatile memory, LED, clock management, keyboard interface, SCI communication units and CAN communication units.
系统的硬件部分主要包括了DSP微处理器的基本外围电路、非易失性存储、LED显示、时钟管理、键盘接口，以及SCI通信和CAN通信等单元电路。
This paper introduces the functions and work principles of serial clock chip DS1302, the design of interface circuit with AT89C51 single -chip microcomputer in the spray irrigation controller.
本文介绍了串行时钟芯片DS1302的功能和工作原理，并给出ds1302在灌溉控制器中与AT 89 C51单片机的接口电路设计。
Mode of serial port pair: synchronous clock device through the serial port read per second pair a serial output time information, serial port and RS232 interface and RS422 interface.
串行口对时方式：装置通过串行口读取同步时钟每秒一次的串行输出的时间信息对时，串行口又分为rs232接口和RS422接口方式。
A new smoothness tester has been designed and accomplished. This paper presents in details the module design of controller, data acquisition, man-machine interface and real clock.
设计了一种新型平滑度仪，详细描述了控制器、数据采集、人机接口和实时时钟等模块的具体选型及设计；
The bus and the processor core often run in different clock frequencies, so their interface signals belong to different clock domains.
总线时钟与处理器内核时钟频率不同，因此总线部件与处理器内核间的接口信号需要进行时钟域转换。
ICS1523 is a high performance programmable line-lock clock generator with the I2C serial bus interface. User can use it to generate desired line-locked clock by programming it.
ICS1523是一种高性能可编程行同步信号发生器，它带有一个I2C串行总线接口，可以方便地对内部寄存器进行配置，能产生用户需要的同步信号。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟进行控制，从而为器件与微处理器或DSP接口创造了条件。
The 2-wire interface is a widely used Master, multi-slave protocol using a serial clock (SCL) and a serial data line (SDA).
此2线接口是一个广泛使用的主机、使用串行时钟（SCL）和串行数据线（SDA）的多从机协议。
The asynchrony FIFO module can be applied in the other asynchrony interface circuit design in multi-clock system.
异步fifo的设计方案对于多时钟系统中异步接口电路的设计具有一定的参考价值。
It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port.
它内置一个低功耗、高速、16位不失码的采样adc、一个内部转换时钟和一个多功能串行接口。
The interface circuit also can produce synchronous, vanished and ensconced, digital clock signal and realize remote control, displaying on screen.
同时产生同步、消隐、数据时钟等信号以及实现遥控、屏幕显示的控制功能。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
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