An 8-bit instruction register can only specify 256 different operations and variations on operations.
一个八位的指令寄存器也只能确定256种不同的操作以及对于这些操作的修改。
Control unit (controller) : control unit is composed of program arithmometer, instruction register and operation controller, ect.
控制器：控制器是由程序计数器、指令存放器跟操作控制器等组成。
Its successor was the 4040 processor (released in 1974), which had an expanded instruction set, program memory, register set, and stack.
其后面是4040处理器(1974发布)，其具有扩展指令集、程序内存、寄存器集和堆栈。
So this instruction stores the link register (which holds the return address) into the proper location in the calling function's stack frame.
所以该指令会将链接寄存器(存有返回地址)存储到调用函数堆栈框架的恰当位置。
An attempt was made to execute a floating point instruction when the floating point available bit in the MSR (machine status register) was disabled.
如果在MSR(机器状态寄存器)中可用的浮点位被禁用，将尝试执行一个浮点指令。
The first instruction does the load and the second instruction rotates the value so that the requested address is at the beginning of the register.
第一个指令负责加载，第二个指令旋转此值以便所请求的地址位于寄存器的开始。
When the function is completed, the value is returned through register 3, and the function exits using the BLR instruction.
当这个函数完成时，返回值会通过寄存器3返回，函数本身使用blr指令退出。
Note that test1 must load and store the global errs value each time it is incremented, whereas test2 stores localerrs in a register and needs only a single instruction.
可以看到test1()中每次加法都需要读取和存储全局变量errs，而在test2()中，localerrs分配在寄存器上，只需要一条指令。
The length instruction determines the length of the string and loads it into an integer register.
length指令确定字符串的长度并将其加载到一个整数寄存器中。
In the following example, the cpuid instruction takes the input in the % eax register and gives output in four registers: % eax, % ebx, % ecx, % edx.
在下面的示例中，cpuid指令采用%eax寄存器中的输入，然后在四个寄存器中给出输出：% eax、%ebx、%ecx、%edx。
BRSL stands for "branch relative and set link." This branches to the function entry point and sets the link register (LR) to the next instruction for the return address.
brsl代表“branch relative and setlink”，用来分支到函数的入口点并将链接寄存器(LR)设置为返回地址的下一个指令。
Important registers to look for when debugging through signals are the GPRs, instruction pointer (NIP), machine state register (MSR), trap, data address register (DAR), and so on.
在调试信号时，需要查看的一些重要寄存器包括GPR、指令指针(NIP)、机器状态寄存器(MSR)、Trap、数据地址寄存器(DAR)等等。
The PowerPC uses a load/store (also called RISC) instruction set, which means that the only time it accesses main memory is for loading into registers or copying a register to memory.
PowerPC使用了加载/存储（也成为RISC）指令集，这意味着访问主存的惟一时机就是将内存加载到寄存器或将寄存器中的内容复制到内存中时。
The rotqby instruction, "rotate (left) quadword by bytes," USES the address you loaded from to indicate how far to rotate the register.
rotqby指令(代表的是“rotate (left)quadwordbybytes”)使用加载自的地址以指示寄存器的旋转程度。
Ila is a special load instruction that loads static addresses, in this case loading the address of the output string into register 3.
ila是加载静态地址的特殊加载指令，在本例中用来将输出字符串地址加载到3。
hbr hint_trigger, $register -- This tells the processor that the branch instruction at the relative address hint_trigger is likely to branch to the address specified in register $register.
hbr hint_trigger, $register ——告诉处理器相对地址 hint_trigger 处的分支指令可能会跳转到寄存器 $register 所指定的地址。
The LK bit specifies whether the address of the next sequential instruction is saved in the Link Register as a return address for a subroutine call.
LK位指定了下一个顺序指令的地址是否作为子例程调用的返回地址保存在链接寄存器中。
The CFG generation process can also be attacked by obfuscating the assembly code such that one cannot determine the correct target of a jump instruction, such as using a jump through register.
攻击CFG生成进程也可以是通过混淆汇编代码以致它不能够正确地确定跳转指令的目标，比如使用寄存器指示跳转目标。
The most common analysis is data dependence analysis, which is to determine the instructions that use the variable (register or memory location) modified by another instruction.
最通常的分析是数据依存性分析，它用来确定指令使用的变量(寄存器或内存位置)是否被另一条指令修改。
The part of execution in which an operand or instruction is read from main storage and written into a control unit or arithmetic unit register.
执行过程中的一个阶段所需的时间，在此期间，计算机从主存储器中取出指令或操作数，并将其存入控制器或运算器的寄存器中。
A register in the processor that contains the address of the next instruction to be executed. Also known as a program counter.
包含下一条要执行指令地址的处理器中的寄存器。也叫程序计数器。
Register allocation and instruction scheduling are two important tasks for every optimizing compiler.
寄存器分配与指令调度是编译器优化过程中的两项重要任务。
This article gives a detail discussion on the assembled code optimization from instruction arrangement, register division, condition selection branch and cycle structure based on the core of ARM9TDMI.
本文基于ARM 9tdmi内核，从指令调整、寄存器分配、条件分支和循环结构等方面对汇编代码的优化方法进行了详细的论述。
This thesis attacks two important issues in back end of an optimizing compiler: instruction selection and register allocation.
这篇论文尝试解决优化编译器的后端中的两个重要的问题：指令选择和寄存器分配。
We also present optimization in instruction scheduling and register allocation phase for this ASIP architecture.
并在指令调度和寄存器分配阶段针对这种ASIP处理器的结构做了优化。
Newly-emerging high performance processors for intensive computing generally use distributed register files to support ALU array and to explore instruction level parallelism(ILP) by VLIW.
新一代面向密集计算的高性能处理器普遍采用分布式寄存器文件来支撑ALU阵列，并通过VLIW开发指令级并行。
Newly-emerging high performance processors for intensive computing generally use distributed register files to support ALU array and to explore instruction level parallelism(ILP) by VLIW.
新一代面向密集计算的高性能处理器普遍采用分布式寄存器文件来支撑ALU阵列，并通过VLIW开发指令级并行。
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