Speculation is a very effective way to improve instruction level parallelism as an advance compiler optimization technique.
投机优化技术作为一种先进的现代编译技术，有效地提高了指令执行的并行性。
Software pipelining is a loop scheduling technique which extracts instruction level parallelism by overlapping the execution of several consecutive iterations.
软件流水是一种开发循环程序指令级并行性的技术，它通过并行执行连续的多个迭代来加快循环的执行速度。
Instruction scheduling is used to exploit the instruction level parallelism (ILP) inherent in program through reordering its instructions.
指令调度通过调整指令之间的顺序来提高指令级并行度(ILP)。
The design problem of an embedded RISC architecture in parallel processing of algorithm level, instruction level and process level is discussed in this paper.
本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题。
In this paper we have proposed instruction level At-speed current testing method taking both the characteristics of microprocessor and At-speed current testing into account.
本文针对微处理器的特点，提出了指令级全速电流测试方法。
The development of instruction level power model is discussed to our self-made LS-RISC microprocessor.
针对笔者自主研制的LS -RISC微处理器，讨论了其指令级功耗模型的开发。
Unless otherwise noted, the instruction level of the education sessions will be intermediate or advanced, appropriate for an experienced, professional audience.
如非另外通知，所有教育研讨会都将是中级或高级的，适合有经验丰富的专业听众。
Newly-emerging high performance processors for intensive computing generally use distributed register files to support ALU array and to explore instruction level parallelism(ILP) by VLIW.
新一代面向密集计算的高性能处理器普遍采用分布式寄存器文件来支撑ALU阵列，并通过VLIW开发指令级并行。
In the designing and exploitation progress of a DSP core, the instruction level simulator can be used in the emulation and debugging, and it is propitious to expedite the rate of development.
在DSP内核的设计、开发过程中，指令级模拟器可用于汇编程序仿真、调试，有利于加快芯片开发进度。
By analyzing factors impacting upon the embedded system performance, an embedded system design method based on thread ideas is used, performance is improved with instruction level parallelism.
通过分析影响嵌入式系统性能的主要因素，采用了基于线程概念的嵌入式系统并行设计方法，利用指令级并行来改善系统性能。
Predication support is one of the new features of IA-64, which offers more opportunities for exploiting instruction level parallelism, however, brings some difficulties for compiler designers.
谓词支持是IA 6 4体系结构的新特征，它为发掘指令级并行提供了更多的机会，同时给编译器的设计者增加了难度。
Several basic blocks could be merged into a hyperblock in predicated execution so that instructions could be scheduled on a larger scope and more instruction level parallelism could be extracted.
谓词执行技术能够将多个基本块合并为一个超块，扩大指令调度范围，开发更多的指令级并行。
This paper presents the implementation approach and the experimental results of multimedia realtime processing on the ILP (Instruction Level Parallelism) computing platform.
讨论了指令级并行运算环境中多媒体数据处理的实现方法和性能。
For years, processor makers consistently delivered increases in clock rates and instruction-level parallelism, so that single-threaded code executed faster on newer processors with no modification.
多年来，处理器制造厂商在不断提高时钟速度和指令级并行性，因此单线程代码不需要修改就可在新的处理器上更快运行。
The big advantages of BCEL are its commercial-friendly Apache licensing and its extensive JVM instruction-level support.
BCEL最大的好处是它的商业友好的Apache许可证及其丰富的JVM指令级支持。
However, this technique also increases the register pressure while it takes advantage of the instruction-level parallelism, and the register spilling is an effective approach to solve this problem.
但该技术在提高指令并行性的同时也增加了寄存器压力，而寄存器溢出技术正是解决寄存器压力的有效方法。
The SWIFT project takes a similar approach but implements a more efficient scheme by reclaiming unused instruction-level resources for the duplicated instructions.
SWIFT项目采用了类似的方法，但实现模式更加有效，它会收回已复制指令未使用的指令级别的资源。
The SWIFT project takes a similar approach but implements a more efficient scheme by reclaiming unused instruction-level resources for the duplicated instructions.
SWIFT项目采用了类似的方法，但实现模式更加有效，它会收回已复制指令未使用的指令级别的资源。
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