Introduction sampling-hold circuit of a pipeline used for ADC.
介绍一种用于流水线adc的采样保持电路。
A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described.
设计了一个用于流水线型模数转换器的低压采样保持电路。
Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.
采样速度和保持精度，是采样保持电路设计制作者最为关注的两项指标。
Track and hold circuit (THA), as the key block of ADC, its linearity directly limits the resolution of the whole system.
跟踪保持电路(THA)作为ADC系统的关键单元，其线性度好坏直接影响着整个系统的精度。
The present application relates also to a method, computer readable medium having a computer program stored thereon and a track and hold circuit comprising the apparatus.
本申请还涉及一种方法、其上存储有计算机程序的计算机可读介质、以及包括该装置的跟踪和保持电路。
On the basis of analyzing the common methods of background magnetic field compensation, a new automatic compensation method based on sample and hold circuit is put forward.
在分析磁通门常用背景磁场补偿方法基础上，提出一种新的采样保持电路自动补偿方法。
The intensity of a pulse emitting laser can be controlled constantly and continuously while recording data without using test emissions or a high speed sample hold circuit.
对在记录数据时处于脉冲发光状态的激光，不用试验发光或高速抽样保持电路，就能经常连续地控制其强度。
The AD9446 is a 16-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use.
AD 9446是一款16位单芯片采样模数转换器(adc)，内置一个片内采样保持电路，专门针对高性能、小尺寸和易用性进行了优化。
The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。
The including imitates the telephone and digital circuits, the simulation telephone is from the operation telephone, sample the hold circuit and defend the saturated telephone constitutive enzyme;
包括模拟电路和数字电路，模拟电路由运算电路、采样保持电路、防饱和电路组成；
Sample the negative voltage on the diode series with IGBT by Peak hold switch circuit, and cut-in A/D module in the DSP, compared with setting value.
通过电压峰值采样保持电路对IGBT串联二极管反压值进行采样，后经DSP A/D转换模块与反压设定值进行比较。
Specify digital circuit timing: setup and hold times and logic propagation delays.
指定数字电路时间∶安装和占用时间和逻辑传播延迟。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
The table with X, Y, Z axes to move, double squeegees with two directions printing, two directions put on the stencil and sure the circuit board can be printing by the through-hold.
台面设有X、Y、Z方向移动、双刮刀双向印刷、双向抬版、双向位移补偿，能确保线路转角夹缝无漏印、贯孔饱满等完美印刷效果。
The table with X, Y, Z axes to move, double squeegees with two directions printing, two directions put on the stencil and sure the circuit board can be printing by the through-hold.
台面设有X、Y、Z方向移动、双刮刀双向印刷、双向抬版、双向位移补偿，能确保线路转角夹缝无漏印、贯孔饱满等完美印刷效果。
应用推荐