• The gate length may be larger than the minimum specified by semiconductor fabrication design rules.

    栅极长度可以比半导体制造设计规则所指定的最小值大。

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  • Under this way, the gate length and thickness of Si island of DG device show many different scaling limits for various elements.

    在这种方法下,由于各种因素的影响,双栅器件的栅长、硅岛厚度呈现出不同的缩减限制。

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  • While the gate length of PHEMT device is adequately short, the parasitic resistance across the width of the gate limits the PHEMT device performance.

    当PHEMT器件的栅长缩短到足够短的时候,沿着栅宽方向的寄生电阻会影响PHEMT器件的性能。

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  • Depending on the potential distribution in the conductive channel, the influence of changing gate length on the OSIT s operation characteristic is analyzed.

    依据导电沟道内的电势分布,分析了栅极长度变化对OSIT工作特性的影响。

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  • The gate length and the dimension of the gate head can be controlled in the T-shaped gate processing, and good process controllability and high yield can be achieved.

    在该T型栅工艺中栅长和栅帽的尺寸分别进行控制,实现了较好的工艺可控性和较高的工艺成品率。

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  • The gate length and the dimension of the gate head can be controlled in the T-shaped gate processing, and good process controllability and high yield can be achieved.

    在该T型栅工艺中栅长和栅帽的尺寸分别进行控制,实现了较好的工艺可控性和较高的工艺成品率。

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