The gate count of a system based on ERCCL can be significantly reduced, which, in turn, will decrease the energy loss.
所以一个基于ERCCL的系统可以大大减少逻辑门数，从而降低系统能耗。
As the average gate count for designs now approaches or exceed on million, the verification has become the main bottleneck in design process.
随着设计规模的不断增加，芯片的平均设计门数已经超越百万级，验证已经成为设计流程中的主要瓶颈。
Adding parallelism typically increases gate count, but the improved computational efficiency allows for the lower clock frequency needed to meet real-time constraints.
添加并行一般通过门数增加来实现，但提高计算效率要求降低时钟频率以满足实时需求。
Both coarse count and fine count which base on the clock and gate delay separately were used to quantify them. Thus, time variable were converted into digital variable.
采用基于门延时的精细计数来量化被测时间间隔中与时钟不同步的部分，这样时间量就被转换成了数字量。
It is shown that the gate-pulse mode reduces the dead time and improves the count rate.
测试结果表明，有源门控模式可以有效缩短死时间并提高计数率。
It is shown that the gate-pulse mode reduces the dead time and improves the count rate.
测试结果表明，有源门控模式可以有效缩短死时间并提高计数率。
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