The main aim of this work is to research the fractional-N PLL in the CMMB application and the realization of the high performance PFD and CP of the PLL.
本文主要研究CMMB系统应用的小数分频PLL以及系统中高性能的鉴频鉴相器和电荷泵的实现。
A fast simulation environment has been developed using MATLAB and SIMULINK for behavioral level simulation of spread spectrum clock generator based Fractional-N frequency synthesizers.
提出了一种展频时钟生成的方法，使用MATLAB和SIMULINK开发出了快速模拟基于分数N型频率合成器的展频时钟生成器的环境。
The operating principle and performance of fractional-N phase locked loop (FNPLL) are described in detail, and the methods of suppressing FNPLL phase modulation sideband are introduced.
较详细介绍了分数分频锁相环的工作原理和特性，以及抑制分数分频锁相环相位调制边带的方法。
Stabilized fractional step algorithm has been widely accepted for numerical solution of the incompressible N-S equations.
分步算法已被广泛应用于数值求解不可压缩n - S方程。
Stabilized fractional step algorithm has been widely accepted for numerical solution of the incompressible N-S equations.
分步算法已被广泛应用于数值求解不可压缩n - S方程。
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