A novel encoding scheme with high speed and low power is proposed for folding and interpolating ADC.
提出了一种新的适用于折叠插值型adc的高速低功耗的编码器。
Bandwidth and offset of CMOS folding preprocessing circuit are the main factors, which limit the dynamic and static characteristics of folding-interpolating ADC.
CMOS折叠预处理电路的带宽和失调是限制折叠内插式adc的动态和静态特性的主要原因之一。
Bandwidth and offset of CMOS folding preprocessing circuit are the main factors, which limit the dynamic and static characteristics of folding-interpolating ADC.
CMOS折叠预处理电路的带宽和失调是限制折叠内插式adc的动态和静态特性的主要原因之一。
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