With a big, easy-to-read flip clock, the date and the weather for your current location are also displayed.
有着大的、易读的翻页时钟，同时还显示日期和你当前位置的天气。
To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.
从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。
According to different sensitive transitions of flip-flops used in sequential circuits, design and analysis methods for asynchronous sequential circuits are proposed by using the combinatorial clock.
本文根据电路中采用的触发器的不同敏感沿，提出采用组合时钟的异步时序电路的设计和分析方法。
The flip-flops are attached to each other in a way so that the output of one acts as the clock for the next, and so on.
触发器以这样的方式相互联接，使一个触发器的输出成为下一个的时钟，依此类推。
Clock regulate the operation of a digital system by allowing time for new results to be calculated by logic gates and then capturing the results in flip-flops.
时钟信号控制着数字系统的操作，它让逻辑门计算新的结果，然后由触发器存储执行结果。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
Especially, the clock-racing multi-threshold flip-flop can decreases the leakage power and the power dissipation of clock network.
特别是多阈值时钟竞争型触发器，不仅可以降低电路的漏电流功耗，还能降低电路的时钟网络的功耗。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
The lead researcher Clifford Saper explains: the neat thing about this second clock is that it can override the main clock... and you should just flip into that new time zone in one day.
这项研究的首席研究员CliffordSaper解释说：第二时钟最妙的地方就在于它可以覆盖我们的主时钟，也就是说你应该可以在一天之内将你的生物钟调整到一个新的时区。
Based on the construction of traditional flip-flop, we propose a novel edge-triggered flip-flip using one latch controlled by narrow pulse according to race-hazard of clock.
在传统触发器结构的基础上，本文提出了单闩锁结构边沿触发器设计，它通过利用时钟信号的竞争冒险产生窄脉冲控制单一锁存器以实现触发器的一次状态转换功能。
Based on the construction of traditional flip-flop, we propose a novel edge-triggered flip-flip using one latch controlled by narrow pulse according to race-hazard of clock.
在传统触发器结构的基础上，本文提出了单闩锁结构边沿触发器设计，它通过利用时钟信号的竞争冒险产生窄脉冲控制单一锁存器以实现触发器的一次状态转换功能。
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