The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.
用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。
Studies issues in the finite state machine (FSM) design in PCI bus interface controllers.
研究有限状态机与PCI总线接口控制器的设计问题。
Moreover, the proposed approach is compatible with state-of-the-art methods for finite state machine (FSM) decomposition, state encoding, etc.
此外，本文提出的方法可以与有限状态机拆分、状态编码和逻辑综合等最先进的优化方法相兼容。
This paper presents a formal approach to specify security model based on the theory of finite state machine(FSM) and the concept of communicating sequential process (CSP).
形式概念分析是从形式背景这一基本的数据形式开始的，因此形式背景的规模是影响概念格构造和应用的一个重要因素。
This paper presents a formal approach to specify security model based on the theory of finite state machine(FSM) and the concept of communicating sequential process (CSP).
形式概念分析是从形式背景这一基本的数据形式开始的，因此形式背景的规模是影响概念格构造和应用的一个重要因素。
应用推荐