This paper provides a scheme of EPP parallel interface controlled by CPLD.
详细介绍了一种在CPLD控制下实现的微型机epp并行接口设计方案。
Making use of EPP parallel interface function of CH341S interface chips, USB current control interface is designed to carry out reading and writing control for the outside equipments.
利用CH341S接口芯片的EPP并行接口功能，可设计usb通用控制接口，以实现计算机控制系统对外设的读写控制。
Finally, the parallel interface in EPP mode is designed and the whole data encryption system designing between FPGA and PC is given to carry out the verification of data encryption results.
论文的最后设计了EPP模式的并行通信接口，实现了pc机与FPGA之间数据加密系统的调试验证。
Based on the properties of Enhanced Parallel Port (EPP), an interface of shift register output has been developed using Complex Programmable Logic Device (CPLD).
基于EPP协议的特点，应用复杂可编程逻辑器件(CPLD)开发了移位寄存器输出接口。
A data measurement system of the eddy current sensor based on the CAN is presented. A parallel interface technology, which enlarges CAN, in EPP mode is mainly discussed.
介绍了一种基于CAN总线的电涡流传感器测试系统，重点研究了EPP模式下并口扩展CAN总线技术。
A data measurement system of the eddy current sensor based on the CAN is presented. A parallel interface technology, which enlarges CAN, in EPP mode is mainly discussed.
介绍了一种基于CAN总线的电涡流传感器测试系统，重点研究了EPP模式下并口扩展CAN总线技术。
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