To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.

从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。

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FPGA is used as trigger source. The data acquisition of precise timing has been realized with edge-trigger manner. Meanwhile, the data analysis is also realized in the system.

系统采用FPGA作为数据采集触发信号源，实现了精确定时的数据采集，同时对采集的数据进行分析和处理。

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FPGA is used as trigger source. The data acquisition of precise timing has been realized with edge-trigger manner. Meanwhile, the data analysis is also realized in the system.

系统采用FPGA作为数据采集触发信号源，实现了精确定时的数据采集，同时对采集的数据进行分析和处理。

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