A fast all digital phase-locked loop with automatic modulus control is presented.
提出了一种具有自动变模控制的快速全数字锁相环。
This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter.
本文讨论的全数字锁相环包括过零检测器和环路滤波器。
The design of precise position tracking loop for DRTS with fast digital phase-locked loop is described.
本文提出一种用于光盘径向伺服系统的带有快速数字锁相环的精密位置跟踪环路的设计方案。
The paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.
本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案。
A specific second-order digital phase-locked loop is modeled after a first-order Markov chain with alternatives, aud analyzed.
按照可列一阶马尔可夫链方式，建立了一个具体的二阶数字锁相环的模型，并对它进行了分析。
All digital Phase-Locked Loop frequency tracking and digital SPWM realization technology based on FPGA are emphasized in the research.
重点研究了基于FPGA的全数字锁相环频率跟踪技术和数字化SPWM实现技术。
It USES a high precision digital phase-locked loop (PLL) to accurately recover the Synchronous reference information of raw cloud-cover image data collected by the geostationary satellite.
它用高精度数字锁相环，精确地恢复地球同步气象卫星采集的原始云图数据的同步基准信息。
This paper presents a new type of all digital phase-locked loop(ADPLL)used for extracting a bit-synchronous signal to meet the requirements of the fast phase-locked in burst digital communication.
本文根据突发式数字通信快速锁相要求，提出一种位同步信号提取的新的快速全数字锁相环方案。
This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS), a method to improve the precision of DDS and reduce its phase truncation error is also given.
介绍了锁相环(PLL)技术和直接数字式频率合成(DDS)技术的基本工作原理，给出了一种提高DDS输出频率精度及减小其相位截断误差的方法。
In the process of signal digital intermediate-frequency received, digital down convertion, frequency tracking of carrier and phase locked loop are the keys.
在信号的中频数字接收过程中，数字下变频、载波频率与相位跟踪是设计的关键所在。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).
本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。
The industrial grating signals can be digital frequency multiplication with a phase-locked loop (PLL) controlled by a microcomputer.
用微型计算机控制锁相环(PLL)可对计量光栅信号进行数字倍频。
The digital very narrow-bandwidth Phase-Locked Loop(PLL) is designed and realized for the digital range and velocity measurement receiver.
本文正是为数字化测速测距接收机设计并实现全数字化超窄带锁相环。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
本文分析了数字锁相环路的寄生频偏，它是现代通讯系统中频率合成器的重要指标之一。
A novel all-digital phase locked loop (PLL), applied to the carrier synchronization of communication systems, is designed.
设计了一种用于通信系统载波同步的新数字锁相环。
Digital thyristor Trigger of High Accuracy is introduced, which is based on phase locked loop synchronization and suitable for dual antistar rectification circuit.
介绍一种高精度数学晶闸管触发器，它基于锁相环同步，适用于双反星形整流电路，并已成功地应用于晶闸管弧焊电流微机控制系统。
The phase locked loop (PLL) frequency synthesizer for digital tuning system(DTS), which is used in DTS of car radio receiver, is presented.
针对一个汽车音响收音数字调谐系统的实例，介绍了一种广播用双波段锁相环频率合成芯片的设计方法。
The principle of voltage linear digital triggering of thyristor by EPROM is described and it is discussed to solve the frequency disturbance on digital trigger by phase locked loop .
描述了用EPROM实现晶闸管电压线性触发原理，讨论了用锁相环解决数字触发的频率扰动问题。
The principle of voltage linear digital triggering of thyristor by EPROM is described and it is discussed to solve the frequency disturbance on digital trigger by phase locked loop .
描述了用EPROM实现晶闸管电压线性触发原理，讨论了用锁相环解决数字触发的频率扰动问题。
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