NOC is a kind of flexible and scalable micro-network on chip, of which the main guild lines are network throughput, delay, resource consumption and power consumption.
NOC是一个弹性的、可扩展的芯片微网络，网络的吞吐率、延迟、资源耗费以及功耗是片上网络重要的性能指标。
The algorithm of CPLD chip designed in this paper, using two pulse-counting and CPLD hardware delay means to achieve the balance between CPLD resource consumption and function.
本文设计的CPLD芯片的算法，采用两级脉冲计数及CPLD硬件延时方法，以达到CPLD资源占用和功能实现的平衡。
FPGA placement and routing is the most time-consuming stage in chip design. To design faster, smaller size, less delay, and low-power algorithm is a very hot research topic.
布局布线是FPGA芯片设计中最耗时的阶段，能够设计出更加快速、更小面积、时延少、低功耗的算法是学术界研究的热点和趋势。
The method takes into account of the uncertainty of the signal delay, thereby the yield of the chip will be improved.
本发明方法充分考虑了信号延迟的不确定性，有利于提高芯片的成品率。
The method of delay chain interpolation is commonly applied in high accuracy time interval measurement, which has the advantages of simplicity and is easy for on chip implementation.
延迟线内插法是一种常用的时间间隔高精度测量方法，具有结构简单、便于片上实现的特点。
This paper puts forward a method of using CMOS chip of delay and ECL gate to generate short pulse, and analyzes the principle of generation.
提出了使用延时芯片和ECL门产生极窄脉冲的方法，并对其产生原理做了理论分析。
Firstly, delay-multiply signal can detect the chip rate and the carried frequency in the frequency domain through multi-autocorrelation.
首先对延时相乘信号进行多重自相关处理，在频域可以检测出信号的码片速率、载频。
Firstly, delay-multiply signal can detect the chip rate and the carried frequency in the frequency domain through multi-autocorrelation.
首先对延时相乘信号进行多重自相关处理，在频域可以检测出信号的码片速率、载频。
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