We propose a second decimation algorithm for widening the range of sweep width in the AD9874 based digital receiver.
基于AD9874 芯片的数字接收机，我们提出了一种扩展数字接收机谱宽的二次抽取算法。
They were the ones mainly responsible for the decimation of North Luangwa's elephant population.
他们应当对北卢安瓜大象数量的大量减少负主要的责任。
In the case of the ivory-billed woodpecker, the wood needed to create our human niches led to the decimation of the Southern old-growth forests that the red-capped bird needed to survive.
在象牙喙啄木鸟的例子中，用木材搭建人类小环境的做法大量毁坏了南部年岁久远的森林——这种红冠小鸟赖以生存的环境。
The last 4 times decimation was achieved by two half band filters and a droop FIR.
剩余4倍抽取采用两级半带滤波器和升幅FIR实现。
The ratio of these two meaningful variables defines the system's decimation ratio.
这两个有意义的变量比例定义了系统抽取比例。
The on-chip decimation filter is configured for maximum performance and flexibility.
该器件配置片内抽取滤波器，可获得最高性能和灵活性。
A strong relationship exists between the decimation ratio and the converter's effective resolution.
抽取率和转换器有效分辨率之间存在一个强大的关系。
CIC filter has proven to be a very effective cell in high-speed decimation and interpolation systems.
CIC滤波器已经被证明是在高速抽取和插值系统中非常有效的单元。
The user has complete control over the filter response, the filter coefficients and the decimation ratio.
用户对滤波器响应、滤波器系数和抽取率拥有完全的控制权。
An on-board digital multiplexer allows the user to access data from the various stages of the decimation filter.
用户可以通过片上数字多路复用器访问各级抽取滤波器中的数据。
A low power, high speed design method of decimation and interpolation digital filters for audio signal processing is described.
介绍一种可用于语音处理的低功耗、高速率的抽取和内插数字滤波器的集成电路设计方法。
Since the decimation of discrete time signals is similar to the sampling of continuous signals, it is also studied in the thesis.
鉴于对离散信号的抽取和对连续信号的采样非常相似，本文还把研究范围拓展到了对离散信号的抽取问题。
This design adopts the algorithm of radix-4 and decimation-in-time (DIT) to devise a real-time FFT hardware processor with practicality.
设计采用基4算法设计了一个具有实用价值的FFT实时硬件处理器。
The digital decimation filter taking the important constituent in the Delta-Sigma Analog-to-Digital converter is realized by the multistage structure.
数字抽取滤波器是它的重要组成部分，通常采用多级结构来实现。
The decimation in time (DIT) radix-2 FFT algorithm is analyzed in details with input in normal order and output in bit-reversed order by the binary method.
运用二进制方法对按时间抽取顺序输入倒序输出的基2FFT算法进行了较为详细的分析和论证。
The converter USES a high order MASH noise shaping technique and a digital decimation filtering part consisting of comb filters and cascade of half band filters.
该转换器采用了高阶MASH噪声成形技术，而其数字抽取滤波部分则由梳状滤波器与级联的半带滤波器构成。
According to the character of FPGA, the FIR digital decimation filter is implemented via using distribution algorithms which are based on the technique of looking up table.
根据FPGA芯片的特点，FIR数字抽取滤波器采用分布式算法来实现，这种方法实现的基础是查找表。
The radix-2 decimation-in-time algorithm based on 16-bit fixed-point operation and pipeline architecture are adopted in the core module IFFT(Inverse Fast Fourier Transform).
核心模块快速傅立叶逆变换（IFFT）采用基于16位定点运算的基-2时间抽取算法和流水线结构。
In addition the device offers programmable decimation rates and the digital FIR filter can be adjusted if the default characteristics are not appropriate to the application.
此外，该器件提供可编程抽取率，而且如果数字FIR滤波器的默认特征不适合应用要求，还可对其进行调整。
This paper studies the parallelism of the different stages of decimation in time radix 2 FFT algorithm, designs the butterfly and scramble kernels and implements 2d FFT on GPU.
本文研究了基2的时域抽取快速傅立叶变换各阶段的并行性，并据此设计了相应的蝶形和倒序运算核，在GPU上实现了二维fft运算。
In addition, the device offers programmable decimation rates, and the digital FIR filter can be adjusted if the default characteristics are not appropriate for the application.
此外，该器件提供可编程抽取率，而且如果数字FIR滤波器的默认特征不适合应用要求，还可对其进行调整。
By utilizing equivalent transformation and polyphase decomposition of the decimation filter, both hardware cost and operating power of each sub-decimation filter were also reduced.
通过利用抽取滤波器的等价变换和多项分解性质，各滤波器级的硬件电路开销和运行功耗都得到了降低。
This paper studies high decimation ratio of digital downconverter given narrow-band signal, and especially analyze mul? stage decimation algorithm based on CIC filter and HB filter.
本文研究了窄带信号条件下，高倍抽取的数字下变频设计，重点分析了基于CIC滤波器和HB滤波器的多级抽取算法。
A programmable decimation and interpolation ratio module onnected with multistage cascade integrator comb (CIC) filter is designed to implement high efficient decimator and interpolator.
将可编程抽取、插值器与多级积分梳状滤波器（CIC）相配合，实现高效数字抽取和插值模块。
This is coupled with unparalleled destruction of habitat for wild animals and decimation of their populations for bush meat, pharmaceuticals, research, entertainment, and other human USES.
野生动物的生活环境遭到空前破坏，加上人类对丛林肉、医药品、研究、娱乐和其他的需求，野生动物的数量急剧减少。
In this paper, the high decimation ratio of digital down converter is studied and the multi-stage decimation algorithm is especially analyzed based on CIC filter, CFIR filter and RRC filter.
研究了高倍抽取的数字下变频设计，重点分析了基于级联积分梳状滤波器、级联补偿滤波器、级联根升余弦滤波器的多级抽样频率算法。
Supply of Blue Mountain coffee has fallen short in the past year or two due to the decimation of farms by past storms, and the inability of uninsured farmers to recapitalise their operations.
在过去的一两年内，蓝山咖啡的产量由于飓风的影响而呈下降趋势，没有保险的农场主没有能力筹措资金恢复生产也是产量下降的因素之一。
Aimed at the existing of minor differences of the signal envelopes, a specific radar emitter recognition algorithm is proposed based on the signal decimation and the maximum-likelihood criteria.
研究了在信号包络存在细微差异前提下，基于信号抽取与最大似然准则的特定辐射源识别算法。
Under certain conditions, combining the polyphase filtering structure of decimation filter, put forward an optimum design method of quadrature demodulation receiver, which owns decimation structure.
结合抽取滤波器的多项滤波结构，在一定条件下，推导出了一种含抽取正交解调接收机最优结构设计方法。
Under certain conditions, combining the polyphase filtering structure of decimation filter, put forward an optimum design method of quadrature demodulation receiver, which owns decimation structure.
结合抽取滤波器的多项滤波结构，在一定条件下，推导出了一种含抽取正交解调接收机最优结构设计方法。
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