We propose a second decimation algorithm for widening the range of sweep width in the AD9874 based digital receiver.
基于AD9874 芯片的数字接收机，我们提出了一种扩展数字接收机谱宽的二次抽取算法。
The last 4 times decimation was achieved by two half band filters and a droop FIR.
剩余4倍抽取采用两级半带滤波器和升幅FIR实现。
The ratio of these two meaningful variables defines the system's decimation ratio.
这两个有意义的变量比例定义了系统抽取比例。
The on-chip decimation filter is configured for maximum performance and flexibility.
该器件配置片内抽取滤波器，可获得最高性能和灵活性。
Design multi-stage decimation system on the basis of Halfband filters and CIC filters.
波带滤波器和CIC滤波器的基础上设计了多级抽取系统。
They were the ones mainly responsible for the decimation of North Luangwa's elephant population.
他们应当对北卢安瓜大象数量的大量减少负主要的责任。
A strong relationship exists between the decimation ratio and the converter's effective resolution.
抽取率和转换器有效分辨率之间存在一个强大的关系。
CIC filter has proven to be a very effective cell in high-speed decimation and interpolation systems.
CIC滤波器已经被证明是在高速抽取和插值系统中非常有效的单元。
Since then, Brandt has documented the extraordinary wildlife of Africa and its unfortunate decimation.
此后，勃兰特记录了非凡的非洲野生动物和其不幸抽取。
The user has complete control over the filter response, the filter coefficients and the decimation ratio.
用户对滤波器响应、滤波器系数和抽取率拥有完全的控制权。
The islands have seen the disappearance of the Hawaiian kingdom, the decimation of its people and language.
这个岛见证了夏威夷王国的消失，人们的大批被杀害和语言的消失。
Multirate Signal Processing: Filtering, Decimation, Polyphase, Perfect Reconstruction and Aliasing Removal.
多速率信号处理：滤波、抽样、多相位、完整重建和去混叠。
The emphasis of research is decimation technology. Design CIC filters and Halfband filters with this theroy.
重点研究了抽取技术，并将这种技术应用于数字中频系统，设计了CIC滤波器和半带滤波器；
An on-board digital multiplexer allows the user to access data from the various stages of the decimation filter.
用户可以通过片上数字多路复用器访问各级抽取滤波器中的数据。
They did all the wiring and decimation of the controller to our system without major changes to our existing system.
他们并没有对现行制度作出重大改变所有的配线及对我们的系统控制器抽取。
The principle of the structures is based on a new concept-multi-interleaving, the generalization of normal sequence decimation.
该结构的原理是基于一种新的概念——多次插排，它是一般的序列插排的推广。
A low power, high speed design method of decimation and interpolation digital filters for audio signal processing is described.
介绍一种可用于语音处理的低功耗、高速率的抽取和内插数字滤波器的集成电路设计方法。
Since the decimation of discrete time signals is similar to the sampling of continuous signals, it is also studied in the thesis.
鉴于对离散信号的抽取和对连续信号的采样非常相似，本文还把研究范围拓展到了对离散信号的抽取问题。
This design adopts the algorithm of radix-4 and decimation-in-time (DIT) to devise a real-time FFT hardware processor with practicality.
设计采用基4算法设计了一个具有实用价值的FFT实时硬件处理器。
The digital decimation filter taking the important constituent in the Delta-Sigma Analog-to-Digital converter is realized by the multistage structure.
数字抽取滤波器是它的重要组成部分，通常采用多级结构来实现。
The decimation in time (DIT) radix-2 FFT algorithm is analyzed in details with input in normal order and output in bit-reversed order by the binary method.
运用二进制方法对按时间抽取顺序输入倒序输出的基2FFT算法进行了较为详细的分析和论证。
The converter USES a high order MASH noise shaping technique and a digital decimation filtering part consisting of comb filters and cascade of half band filters.
该转换器采用了高阶MASH噪声成形技术，而其数字抽取滤波部分则由梳状滤波器与级联的半带滤波器构成。
This method proposes five decimation patterns based on the gradient descent direction, and it can select the decimation pattern adaptively during the motion estimation.
首先改进传统的一维梯度下降搜索算法，并提出由梯度下降方向自适应选择不同的抽取模式去除计算运动估计准则时的冗余。
A mathematical model of DTV broadcasting signal has been set up before reviewing theories of multistage decimation and stating the algorithm of moving target detection.
叙述了数字电视广播信号回波的数学模型、多级抽取基本原理和目标检测算法。
According to the character of FPGA, the FIR digital decimation filter is implemented via using distribution algorithms which are based on the technique of looking up table.
根据FPGA芯片的特点，FIR数字抽取滤波器采用分布式算法来实现，这种方法实现的基础是查找表。
Emphasized on the design of multilevel decimation and multilevel interpolation, devised many schematics to simplify the design and made the design approaching optimization.
重点讨论了多级抽取和内插滤波器的设计，绘制了大量的图表使它们的设计简单明了且接近最优。
The radix-2 decimation-in-time algorithm based on 16-bit fixed-point operation and pipeline architecture are adopted in the core module IFFT(Inverse Fast Fourier Transform).
核心模块快速傅立叶逆变换（IFFT）采用基于16位定点运算的基-2时间抽取算法和流水线结构。
In addition the device offers programmable decimation rates and the digital FIR filter can be adjusted if the default characteristics are not appropriate to the application.
此外，该器件提供可编程抽取率，而且如果数字FIR滤波器的默认特征不适合应用要求，还可对其进行调整。
This paper studies the parallelism of the different stages of decimation in time radix 2 FFT algorithm, designs the butterfly and scramble kernels and implements 2d FFT on GPU.
本文研究了基2的时域抽取快速傅立叶变换各阶段的并行性，并据此设计了相应的蝶形和倒序运算核，在GPU上实现了二维fft运算。
This paper studies the parallelism of the different stages of decimation in time radix 2 FFT algorithm, designs the butterfly and scramble kernels and implements 2d FFT on GPU.
本文研究了基2的时域抽取快速傅立叶变换各阶段的并行性，并据此设计了相应的蝶形和倒序运算核，在GPU上实现了二维fft运算。
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