AGI could, its advocates say, work for us around the clock, and drawing on all available data, could suggest solutions to many problems.
那些拥护通用人工智能的人说，它可以全天候为我们工作，利用所有可用的数据，为许多问题提出解决方案。
A real-time clock circuit(X1228)is applied to be an hourmeter, data memorizer and alarm in speedometer.
实时时钟电路（X1228）被用作里程表，数据存储器和车速表中的警报。
In addition to a typically recorded transaction, many innocuous objects, such as parking lots, buildings, and street corners, are instrumented and record large volumes of data around the clock.
除了通常记录的交易之外，许多不活动的事物也被全天不间断地记录下来，比如停车场、建筑物和街道角落，这样数据量就会变得非常大。
Depending on how the researchers calibrated their clock, the data point to an origin of domesticated rice around 8, 200 years ago.
通过科研人员校对“分子钟”，数据显示出该驯化水稻在大约8200年前的原始稻种。
In the cases where there is data with data type TIME that doesn't fit into the 24-hour clock, normalize the data to be compatible with the DB2 data type in MySQL before migration.
对于那些不符合24小时格式数据类型TIME的数据，我们需要在迁移之前将它们规范化为MySQL中兼容db2的数据类型。
Some devices have two clocks, one to "capture" or "display" data, and another to clock it into the device.
一些设备有两个时钟，一个用于“捕获”或者“显示”数据，另一个则用于提供将数据输入器件的时序。
This makes possible to control the plural flows of data even with the considerable increase for clock frequency.
这使得能够控制复数流动的数据，甚至与相当的增加时钟频率。
The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟信号进行控制，从而为器件与微处理器或DSP轻松接口创造了条件。
Sending data from slave to master may use the opposite clock edge as master to slave.
数据从主机发给从机可能会使用与从机发给主机相反的时钟沿。
In binary synchronous communication, the use of clock pulses to control synchronization of data and control characters.
在二进制位同步通信中，使用时钟脉冲来控制数据和控制字符的同步。
In order to accomplish the data process and conversion, the clock generation circuit, 100% modulation signal and 10% signal demodulation circuit are designed.
为了完成数据的处理和交换，分别设计了时钟产生电路、100%调制信号和10%调制信号的解调电路。
Simulation of relative delays between Data and Clock pulse trains in 0.1 microseconds increments to 3.1 microseconds.
对于数据和时钟脉冲列之间的相关延迟的模拟，以0.1微秒为递增单位增加到3.1微秒。
The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟进行控制，从而为器件与微处理器或DSP接口创造了条件。
This instrument based on LPC932 as the key microprocessor to gather , deal with and store data, to control real-time clock, to complete the liquid crystal display and communication.
该仪器基于LPC932单片微机为核心微处理器，来完成数据采集、处理，存储，实时时钟控制，液晶显示，通信等功能。
A kernel structure is presented, which adopts data fusion to support precision-demanding clock synchronization tasks.
该内核结构采用数据融合加强对精度要求较高的时钟同步任务的支持。
For substation layer, a feasible strategy for bad data grading handling and a practicable method to establish the uniform clock for the power network were put forward.
对于厂站层，论文提出了对不良数据分级处理和建立全网统一时钟的策略和方法。
To reduce the pattern effect in all-optical clock recovery, a novel device termed as code mixer was designed to preprocess the injected data signals.
为减少全光时钟提取中的码型效应，设计了混码器对注入数据脉冲进行预处理。
The three key technologies of tobacco toasting autocontrol system are to be realized stably temperature collecting, to be protected data after turn-off, and real time clock function.
烟叶烘烤自动控制系统的三大核心技术是实现稳定的温度采集、掉电保护、实时时钟功能。
That is, 30-hour chunks of data (which may span 40 hours of clock time due to dropouts) which require a search of a spindown parameter as well as sky position. But nothing is set in stone.
也就是30小时的大段数据（由于含有无效信息可能会扩展到40小时），这与天区位置有关。
Especially in the bus design on the backplane, we should pay more attention to the distribution, interconnection of the clock, data line.
背板上的总线时钟和数据线的分布，互连设计显得尤为重要。
Engineers based at the Schlumberger ALSC in Russia analyzed data and monitored threshold alerts to prevent and troubleshoot adverse ESP events around the clock.
在斯伦贝谢的俄罗斯alsc，工程师全天候分析数据，监控阈值报警器，以预防并解决出现的ESP故障。
Lastly, the clock speed of the bus feeding scan chain data to the pins of the DUT is increased by multiplexing the scan chain data being transferred to the bus.
最后，通过多路传送被传输到总线的扫描链数据，可以提高输送扫描链数据到DUT管脚的总线的时钟速度。
If a sign has a refresh rate of 100 Hz, then it must clock out 128 bits of data for one line of LEDs from left to right, 100 times per second.
如果标识的刷新频率为100hz，那么它必须在一行发光二极管中，从左到右以每秒100次的速度输出128位数据。
The clock device setting of the differential protection affects the data communication, and in order to reduce the influences, the optimal clock settings for different channels should be used.
差动保护装置时钟设定影响通信数据，为尽量减少误码对差动保护的影响，应根据不同的通道方式，采用不同的最佳时钟设置。
This Design Idea describes how to implement a common clock (synchronous version) for an FPGA-based FIFO for data-width conversion with different-width read and write data ports.
本设计方案描述了为不同宽度读写数据端口的数据宽度转换，怎样基于FPGA的FIFO实现共有时钟(同步)。
Cl stands for "CAS latency," which is the number of clock cycles it takes before data starts to flow once a command is received.
CL是指“CAS延迟”，是指收到命令以后，再数据开始传输以前，所需要的时钟周期的数量。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
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