At the Synthesis stage, we select the Top Down compile strategy, and suppose an ideal clock.
综合阶段采用的是自顶向下的编译策略，并虚拟理想时钟。
Using clock as data has created various issues in timing closure, particularly in logic and physical synthesis.
使用时钟作为资料在定时关闭已经创造各式各样的问题，特别在逻辑和物理综合。
The synthesis results show this FFT structure can run at 52mhz clock rate in XC4025E - 2. This FFT structure is easy to expand more points FFT structure.
从综合的结果看该结构可在XC 4025e-2上以52mhz的时钟高速运行。在此基础上易于扩展为大点数fft运算结构。
Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
The direct digital synthesis (DDS) is adopted to generate the pseudo-random code clock having high precision and stability.
利用直接频率合成技术产生高精度、高稳定度的扩频伪码时钟。
The correct test results of the chip also verify the effectiveness of this clock tree synthesis program.
芯片测试结果的正确也验证了这种时钟树综合方案的有效性。
Offering direct digital frequency synthesis (DDFS) based on the frequency -phase to achieve the following sampling clock.
提出基于频相的直接数字频率合成技术（DDFS）实现采样的跟随时钟。
Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.
实验结果表明：按权重分配裕量的方法相对于平均分配裕量，能够在不降低电路性能的情况下，更加有效地降低逻辑综合结果的面积。
The results indicate that, compared with the results obtained by the automatic clock tree synthesis, better results can be obtained by the proposed method.
结果表明，用文中方法设计时钟树结构能得到比自动时钟树分析更好的效果。
The results indicate that, compared with the results obtained by the automatic clock tree synthesis, better results can be obtained by the proposed method.
结果表明，用文中方法设计时钟树结构能得到比自动时钟树分析更好的效果。
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