A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
The invention furthermore provides that the clock patterns are selected taking into consideration a phase selection for the current measurement.
此外规定在考虑针对电流测量的相选择下选择该节拍模式。
The invention furthermore provides that the clock patterns are selected taking into consideration a phase selection for the current measurement.
此外规定在考虑针对电流测量的相选择下选择该节拍模式。
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