A single clock input is used to control all internal conversion cycles.
采用一个单时钟输入来控制所有内部转换周期。
A single-ended clock input is used to control all internal conversion cycles.
采用一个单端时钟输入来控制所有内部转换周期。
An external clock is a common solution but it requires a digital source equipped with clock input, it exists but it is rare and specific.
(增加)外部的时钟是通常的解决方案，但这要求数字源设备具有时钟输入接口。
This will be the input for the external clock.
这将作为外部时钟的输入端。
Another example is designing a system that gets the date from the internal clock instead of asking for input from users.
另一个例子是设计从内部时钟获取数据的系统，用来取代请求用户输入。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
Its function is to provide a latching switch action upon sensing an input threshold voltage, with reset accomplished by an external clock signal.
它的功能是当感应到输入电压界限时提供一个锁存开关，通过外部时钟信号完成复位。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
At first blush, you might think that you could simply cascade two counters together using the carry-out pin, Pin 12, from one counter to feed the clock-input pin, Pin 14, of a second counter.
初看上去，也许会考虑使用动作管脚（管脚12）从一个计数器接到第二个计数器的时钟输入管脚（管脚14），简单的级联两个计数器。
Based on the system clock and trigger input signals, using FPGA to generate trigger output signals in given working modes.
通过FPGA实现在一定系统时钟和触发信号作用下各种工作模式的触发信号的产生。
The system use input clock as system clock and use parallel structure in system to provide flexible speed.
全系统采用输入数据的同步时钟作为系统时钟，系统内部采用全并行的方式，以提供灵活的速度。
Input clock frequency of 500hz, the time for lights between 1-4 seconds, they can control.
输入时钟频率为500hz，灯亮的时间在1—4秒之间，可以自由控制。
The clocking circuit configured to provide the pull-up current to an internal node in response to a clock signal having the input supply voltage and the ground voltage.
时钟电路被配置为响应于具有输入供电电压和接地电压的时钟信号向内部节点提供上拉电流。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
The reference capacitor can charge at a third clock phase, thus the input signal is released from the capacitor dependently from the voltage.
参考电容器可以在第三时钟相位放电，这样输入信号依赖电压从电容器被释放。
The reference capacitor can charge at a third clock phase, thus the input signal is released from the capacitor dependently from the voltage.
参考电容器可以在第三时钟相位放电，这样输入信号依赖电压从电容器被释放。
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