In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
Check your clock; more importantly, look at the dates of files in your build tree, and other files on your system, and your clock.
检查系统时钟；更重要的是，要检查编译树中文件的日期、系统中其他文件的日期以及系统的时钟。
In designing synchronous digital integrated circuits, the design of clock tree is an important component, which may greatly affect the performance and reliability of the system.
时钟树的设计是同步数字集成电路设计中的一个重要部分，对系统的性能和可靠性有很大影响。
The correct test results of the chip also verify the effectiveness of this clock tree synthesis program.
芯片测试结果的正确也验证了这种时钟树综合方案的有效性。
A binary tree routing topology is designed for propagating the system clock and trigger signal and the accurate timing and synchronization between sensors are provided by CPLD.
设计了二进制树型拓扑结构传播统一的系统时钟和触发信号，采用CPLD提供传感器间的精确时序和同步。
Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
In order to reduce the power in the clock tree, a new gating circuit is presented.
为了能够减少时脉系统的功率消耗，一种新型的闸电路被提出。
In order to reduce the power in the clock tree, a new gating circuit is presented.
为了能够减少时脉系统的功率消耗，一种新型的闸电路被提出。
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