Secondly, controller design of NCS for delay compensation is studied when the controller is clock-driven.
其次，研究了控制器为事件驱动时网络控制系统的时延补偿控制。
The earliest recorded weight-driven mechanical clock was built in 1283 in Bedfordshire in England.
有记载的最早的重量驱动机械钟是1283年在英国贝德福德郡建造的。
Scientists had thought that the circadian clock was driven by gene activity, but both the algae and the red blood cells kept time without it.
科学家认为生物钟是受基因活动影响，但是藻类和红细胞没有基因也同样按照生物钟运行。
Scientists had previously thought the circadian clock was driven by gene activity, but both the algae and the red blood cells kept time without it.
科学家们曾认为昼夜节律的调节是受基因活动支配，但海藻和红细胞中都不含DNA。
A yield driven clock skew scheduling algorithm is proposed in presence of process variations.
针对工艺参数变化的情况，提出一种成品率驱动的时钟偏差安排算法。
The latter takes PWM (Pulse-Width Modulation) control and ZVS control as its target, synchronizes with clock to realized its driven waveform. In addition, adaptive dead-time control is analyzed.
由程序综合的控制电路以PW M控制和ZVS控制为目标，并由时钟同步，实现了对驱动波形的控制。
The effects of multiplicative noise on additive noise-induced internal signal stochastic resonance(ISR)are studied in a Neurospora circadian clock system driven by external signal or not.
利用有和无外信号作用的脉孢菌生物钟体系，研究了与加性噪音相关或不相关的乘性噪音对加性噪音诱导出的内信号随机共振的影响作用。
The release of ACTH by the pituitary gland at the base of the brain is driven by a third hormone that is activated by the body's master clock.
身体的主时钟基础状态下激活另外一种激素刺激由脑垂体释放ACTH。
Many clock circuits also work with a resistor and capacitor as low-cost timing components or can be driven from an external source.
许多时钟电路也与电阻器和电容器一起使用作为低成本的时间组分或驱动外部输入。
I remember a student named Sam who often popped by our clock tower living room for after-dinner chats, driven by curiosity about the outside world, quietly amassing ideas and opinions.
我记得有个叫萨姆(sam)的学生经常出现在我们在钟楼的起居室，想在晚饭后聊聊天，因为他对外面的世界很好奇，在悄悄地搜集思想和观点。
Most of the ASIC" s ever designed are driven by multiple asynchronous clocks. An important problem in multi-clock do-main design is how to avoid metastability."
绝大部分ASIC设计工程师在实际工作中都会遇到多时钟域设计的问题，多时钟域设计的一个难题是如何避免亚稳态的产生。
Most of the ASIC" s ever designed are driven by multiple asynchronous clocks. An important problem in multi-clock do-main design is how to avoid metastability."
绝大部分ASIC设计工程师在实际工作中都会遇到多时钟域设计的问题，多时钟域设计的一个难题是如何避免亚稳态的产生。
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