Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured.
为了克服制程、电压、温度变异所造成的影响，自动时脉偏移同步方案可以在晶片制造出来之后动态地调整并降低时脉偏移。
To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured.
为了克服制程、电压、温度变异所造成的影响，自动时脉偏移同步方案可以在晶片制造出来之后动态地调整并降低时脉偏移。
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