Sometimes a fast, inexpensive CPU can become expensive once bus logic and the delays necessary to make it work with other peripherals are considered.
有时，一旦把CPU使用其它外围设备所必需的总线逻辑和延迟时间考虑在内，那么快速而廉价的CPU也可能变得昂贵。
The handling (or routing) of a message is managed by the bus and does not clutter any business logic.
消息的处理(或路由选择)是通过总线做到的，并且没有扰乱任何业务逻辑。
Thus, it is fair to say that mediation (and thus the service bus) can contain business logic, but only if it is non-semantic.
因此，中介(和服务总线)可以包含业务逻辑，但是这些逻辑只能是非语义的。
Based on the above descriptions of the integration layer and the service bus, you recognize conflicts; for example, business logic is a form of integration logic.
根据前面对集成层和服务总线的讨论，您可以看出矛盾之处；例如，业务逻辑是集成逻辑的一种形式。
We further showed the service exposure layer can contain only non-semantic logic, but that includes business-owned non-semantic logic, thus allowing business logic in the service bus (ESB).
服务公开层只能包含非语义逻辑，但是其中包括业务拥有的非语义逻辑，因此在服务总线(esb)中可以有业务逻辑。
The logic design and physical implementation of a GPIO_WB controller based on WISHBONE Bus are achieved.
完成了一种基于WISHBONE总线的GPIO_WB控制器的逻辑设计和物理实现。
Except for the analogue controlling and bus driving devices, we use FPGA to implement controlling logic in order to provide expansibility of application platform.
在设计上除模拟控制及总线驱动等器件外，尽量采用FPGA来实现控制逻辑以提供应用平台的可扩展性。
To avoid interfering by work, data were sampled through a multi-layers network which synthesize the field-bus and Ethernet and center on programmable logic controller.
为了排除人为干扰、提高可靠性，采集数据以可编程逻辑控制器为核心，通过现场总线和以太网的多层网络传送至数据库中。
The method which integrates PCI bus interface and control logic into a FPGA chip improves the integration density and transplantation of system.
该方法将PCI总线接口和控制逻辑集成于一片FPGA中，提高了系统的集成度和可移植性。
Making use of logic analyzer, oscillograph and bus analyzer, we can design and test the superhigh density FPGA, and transmit the signal to the instrument through probe and linker.
设计和验证超高密度FPGA的方法是采用逻辑分析仪、示波器和总线分析仪，通过测试头和连接器把信号送到仪器上。
This paper introduces the design and realization of a high-speed and low-cost virtual logic analyzer based on FPGA and USB2.0 bus.
本文介绍了一种基于FPGA的USB2.0高速、低成本的虚拟逻辑分析仪的设计原理与实现方法。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
访问内部统一二级处理器缓存的后端总线接口逻辑。
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data.
数据总线上的输入数据是否写入存储器，取决于此时的DM的输入逻辑。
Practical application shows that the bus arbitration logic mentioned above is characteristic of low arbitration overhead, fine scalability and higher reliability.
实际运行表明：该仲裁逻辑电路具有仲裁开销小、扩缩性好、可靠性高等特点；
The paper presents 4 kinds of action logic of bus-bar automatic transfer switch equipment for whole inner-bridge connection.
介绍了完整内桥接线情况下备自投装置的4种动作逻辑。
On a graphic logic SW platform, different automatic bus transfer schemes can be realized on a graphic logic software frame, which features hing efficiency, flexibility and re-liability.
结合图形化逻辑软件平台，展示了图形化逻辑在实现各种备自投方案所具有的灵活、高效的特点。
The product is specifically designed to provide well-regulated supply for low voltage IC applications such as high-speed bus termination and low current 3.3v logic supply.
本产品专门设计用于提供规则电源，主要是为低压ic应用：如高速总线终端和3.3V低电流逻辑电源等供电。
A fiber field-bus communication system based on complex programmable logic devices (CPLD) and optical transceiver was designed for some special industrial fields such as colliery and airfields.
针对煤矿、机场等特殊工业现场，设计了一种基于复杂可编程逻辑器件(CPLD)和光模块的光纤现场总线通讯系统。
The logic elements in controller are multiple CPU network setup. Individual intelligent functional modules are interconnected by CAN bus for data exchanging and multiple CPU cooperating.
控制器的逻辑单元为多cpu网络体系，体系内各智能化功能模块通过CAN总线互联，实现模块间的数据交换和多cpu协同工作。
The dissertation introduces not only PCI bus protocol and PCI9054 in detail, but also the FPGA logic design.
FPGA作为控制核心，其逻辑程序设计也是本文重点介绍的对象。
The architecture and logic of chained arbitration-bus, the design idea of communication software, and the diagrams about transmitting and receiving are given.
描述了CMMS系统结构及总线仲裁链式环逻辑，介绍了通信软件设计思想，并给出了发送和接收程序流程图。
All CAN nodes linked by CAN bus cooperate with each other to fulfill control logic in the industrial distributed embedded control system.
在工业分布式嵌入式控制系统中，系统工艺要求达到的控制目标是由系统中各个CAN节点协调工作而实现的。
All CAN nodes linked by CAN bus cooperate with each other to fulfill control logic in the industrial distributed embedded control system.
在工业分布式嵌入式控制系统中，系统工艺要求达到的控制目标是由系统中各个CAN节点协调工作而实现的。
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