The interface enables you to look at buses defined at the cell level, then drill down to view queue points, publication points and mediation points on the bus.
该界面使您可以查看在单元级别定义的总线，然后展开以查看总线上的队列点、发布点和中介点。
This scheme includes three parts: PCI Bus interface board, experiment flat board and device driver high-level software.
该设计方案由PCI总线接口板、实验平台板、设备驱动程序及上层软件三个部分组成。
This scheme includes three parts: PCI Bus interface board, experimental platform device driver and high-level software.
该设计方案由PCI总线接口板、实验平台板、设备驱动程序及上层应用软件三个部分组成。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
访问内部统一二级处理器缓存的后端总线接口逻辑。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
访问内部统一二级处理器缓存的后端总线接口逻辑。
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