The utility model relates to an assembly used in a door of a vehicle, particularly, a buffer unit for opening a vehicle door.
本实用新型涉及一种用于汽车车门上的组件，具体来说是一种车门开启缓冲装置。
The present invention also discloses a device for transmitting a compressed coding result of video, which includes: a buffer unit, a coding unit, a FIFO and a transmission control unit.
本发明还公开了一种传输视频压缩编码结果的装置，包括：缓存单元、编码单元、FIFO和传输控制单元。
If set to 1, the modem will accept data and buffer it until the unit is synchronized.
如果设置为1，调制解调器将接收数据并存入缓冲区，直到单元同步。
Only one input of the digital circuit unit is the buffer or inverter, the input in more than one are called logic gates.
只有一个输入的数字电路单元是缓冲器或反相器，而输入在一个以上的则称为逻辑门。
A portion of the buffer cycle in which the logic or arithmetic unit must cease operation or neither will be able to communicate with the memory unit.
缓冲存储器周期的一部分，在这期间，逻辑与算术运算器必须中止操作或不能与存储器传输信息。
The improved model of input buffer presented is to insert a quasi random memory between input queue and arbitration logic at ATM switching unit.
改进的输入缓冲方案是在AT M交换单元的输入队列和仲裁逻辑之间加入一个准随机存储器。
The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.
其中包括地址缓冲、译码器、存储单元、灵敏放大器和输出缓冲电路。
The encoding unit, composed of instruction buffer and command encoder, translates the 12-bit command code to 16-bit control signal, and ensures each part of the system to work steadily.
译码单元由指令缓存器和指令译码器构成，针对12位的指令代码翻译成16位控制信号，传送给处理器内部各个部件，用以保证各部件正常工作。
Each processing module may include a network interface, at least one buffer, a packet parser, a packet builder, and at least one processing unit.
每一个处理模块都可以包括网络接口、至少一个缓冲器、分组解析器、分组构造器和至少一个处理单元。
The cable monitoring module is connected to the central unit via the sitras pro baplus dc buffer amplifier and is powered by the contact line voltage .
另一个可选控制功能是对基于测得电压接触线电压及测试电流的剩余区间电阻进行计算。
The storage unit, the current detector, the Schmidt buffer, the inverter (1) and the inverter (2) are connected in sequence.
储存单元、电流检测器、施密特缓冲器、反相器1、反相器2依次相连接。
That means the IGBT-based switch unit switches from one position to the other depending from the filling status of the buffer and the operation mode of the load.
这意味着，依赖于缓冲器的填充状态和负载的操作模式，基于IGBT的开关单元从一个位置切换到另一位置。
Arithmetic unit: arithmetic unit is a data processing unit that consists of arithmetic logic unit (ALU), accumulator, data buffer, ect.
运算器：运算器是数据加工处理部件，它是由算术逻辑单元(alu)、累加器、数据缓冲器等组成。
It is preferably, that the inrush current limiter device further comprises a chargeable capacitive buffer, arranged downstream in regard to the IGBT-based limiter unit for forming a buffered output.
优选的是，浪涌电流限制器设备进一步包括可充电电容缓冲器，其设置在关于基于IGBT的限制器单元的下游，用于形成缓冲的输出。
The capacitive DC buffer serves as a high frequency decoupling unit and is formed by a corresponding capacitor.
该电容DC缓冲器用作高频去耦单元，并且由对应的电容器形成。
The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.
FPGA实现MV B控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。
During the bending processing, the bending buffer distance piece (42) can easily realize the bending and greatly ensures the performance of the core unit.
在弯曲处理过程中，弯曲缓冲间隔件(42)使弯曲容易进行并且极大地保证了芯单元的性能。
Based on the single buffer copy technology, the strategy overcomes the inefficiency of storage block copy in some embedded system's memory control unit.
该策略基于缓冲区单次拷贝技术，克服了有些嵌入式系统存储控制器低效的存储块拷贝。
Based on the single buffer copy technology, the strategy overcomes the inefficiency of storage block copy in some embedded system's memory control unit.
该策略基于缓冲区单次拷贝技术，克服了有些嵌入式系统存储控制器低效的存储块拷贝。
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