The design of the buffer circuit of the IGBT is studied.
对IGBT缓冲电路设计进行了分析。
A lamp tube driving circuit includes transformer and buffer circuit.
一种灯管驱动电路，此灯管驱动电路包括变压器与缓冲电路。
The output buffer circuit can reduce spikes of waveforms in the readout circuit.
输出缓冲电路可以削减读出电路中所产生的波形尖峰。
A hysteresis adding circuit (75) is coupled to the at least one output of the buffer circuit.
磁滞添加电路(75)连接到缓冲电路的所述至少一个输出端。
The optimum problem of the buffer circuit is analyzed about the propagation delay, the integrated circuit area and the power consumption.
针对其时间延迟、晶体面积和功率散逸影响的效率问题做最佳化的分析。
The television power supply demands low ripple voltage, and the passive rc buffer circuit used in television before, decreased the power effect.
电视机电源要求非常低的纹波电压，过去电视机所采用的是大的无源rc缓冲电路，使电视机的电源效率比较低下。
Four modules are included in the SPDT analog switch, for example, MOS switch circuit, driver circuit, buffer circuit, and ESD protection circuit.
单刀双掷模拟开关电路的设计包括四个模块：MOS开关电路、驱动电路、缓冲电路和ESD保护电路。
Based on the detailed analysis of the loading properties of a medium or small size TFT-LCD driver IC, a novel output buffer circuit of driving voltages is proposed.
在分析中小屏幕TFT - LCD驱动芯片的负荷特性的基础上，提出了一种新型的驱动电压输出缓冲电路结构。
Secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc.
详细叙述了通讯板接口模块的硬件结构设计，其中，对数据缓冲电路、数据传输速率选择电路、逻辑控制电路等各关键点做了重点介绍；
This limiting amplifier composed of an input buffer, amplifier cells, output cells, and offset cancellation circuit.
此限幅放大器由输入缓冲、主放大单元、输出缓冲、偏置补偿电路四部分组成。
It proposes using a noninverting amplifier consisting of a high accuracy and low drift integrated operational amplifier OP. 07 as a buffer amplifier in the circuit.
提出用高精度低漂移集成运算放大器OP-07组成同相放大器，作为监测电路的缓冲放大器；
Only one input of the digital circuit unit is the buffer or inverter, the input in more than one are called logic gates.
只有一个输入的数字电路单元是缓冲器或反相器，而输入在一个以上的则称为逻辑门。
An output buffer amplifier with compact structure used in detection circuit of micro sensor is presented.
设计了一种主要用于微传感器读出电路的输出缓冲放大器。
This paper describes the implementation of buffer manager that is used in switch circuit, provides a request shift method to handle the latency between input buffer and central arbitration.
研究了交换控制电路中基于输入缓冲的交换结构，提出了一种请求移位的方法处理输入缓冲和中央仲裁器之间的仲裁延时；
It uses tow-stage differential amplifiuers to increasee the circuit gain and uses a source follower as a voltage buffer to decrease signal volt- age losing.
该电路应用两级差动放大增加电路增益，利用源极跟随器作为电压缓冲器以减少信号电平损失。
The protocol realized some functions, such as two-way data buffer, shift register, clock circuit and parity check.
在通信协议中，主要实现了双向数据缓冲器、数据移位寄存器、时钟控制电路以及奇偶校验等功能。
Hysteretic current controllable voltage source inverter technology and single phase clamping buffer technology used in the system were introduced; the power circuit and control circuit were designed.
系统中采用了滞环电流可控电压型逆变器技术与单相箝压缓冲技术，并对功率主电路与控制电路进行了设计。
The analog part includes self-test circuit, charge amplifier, post-amplifier circuit, CDS and S/H circuit, integrator, unity gain buffer.
该电路的模拟部分包括电荷放大器、后级放大电器、相关双取样与采样保持电路、积分器、单位增益缓冲器。
The interface uses a circuit based on dual port FIFO buffer memory to realize data transfer of different I/O velocity between the two computers.
该接口采用双端口FIFO缓冲存储技术，实现两机间不同I／O速度的数据通信。
Parameters of main power devices which include diode, IGBT, capacitor, inductance and buffer snubber circuit have been calculated in main circuit in the article.
本文还对主电路主要功率器件进行了参数计算，包括二极管、IGBT、电容、电感、缓冲吸收电路参数等。
This paper describes the design of a variable impedance output buffer, and its adaptive control circuit. It can automatically adjust the impedance of output buffer in real-time.
本文设计了一个阻抗可变的输出驱动器，并配套地设计了自适应的阻抗控制电路，能在电路工作中实时调节输出阻抗。
A novel frame buffer pixel circuit was developed which acquires low power inside a pixel.
开发了一种新型的帧存储像素电路结构，实现了像素内低功耗。
A novel frame buffer pixel circuit was developed which acquires low power inside a pixel.
开发了一种新型的帧存储像素电路结构，实现了像素内低功耗。
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