SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.
边界扫描技术是一种标准的数字电路测试及可测试性设计方法，它在工业界得到了广泛的应用。
With the continual improvement of the chip's integration level and complexity of print circuit board, the application of boundary scan test technology becomes wider and wider in testing ICs.
随着芯片集成度和印刷电路板复杂度的不断提高，边界扫描测试技术在芯片故障检测中的应用越来越广泛。
The miniaturization of electronic products results in automatic testing, which is made possible by boundary scan technology.
电子产品微型化使自动测试成为必然，而边界扫描技术则使自动测试成为可能。
Combining boundary scan with functional test, expanded application of boundary scan and larger testing coverage may be realized.
边界扫描技术与功能测试的结合，可以扩展边界扫描技术的应用范围，实现了更高的测试覆盖率。
The automatic testing software which is compatible with BSDL files and EDIF files can complete multiple boundary scan test tasks.
兼容于BSDL和EDIF文件格式的自动测试向量生成软件可实现多种扫描测试功能。
Joint test Action Group designed a common chip boundary-scan structure and test access port criterion which is called JTAG standard to support testing on-board chip or logic.
为支持板上芯片或逻辑的测试，联合测试行动小组专门设计和定义了一种通用的芯片边界扫描结构及其测试访问端口规范，称为JTAG标准。
Many in-circuit testers now have boundary-scan test capability. With boundary-scan testing, you can test interconnections on PCBs without using a probe on each node.
很多测试设备具有分界扫描的功能，这样，测试人员就可以直接测试印刷电路板上的互连，而没用必要使用探针去测试每一个节点了。
Meanwhile the testing of SOC become more difficult and complex, Boundary-Scan-based Built-in-Test technology give a new solution.
与此同时，片上系统的测试问题也随之产生，基于边界扫描的内建自测试技术为片上系统的测试提供了新的解决方案。
Meanwhile the testing of SOC become more difficult and complex, Boundary-Scan-based Built-in-Test technology give a new solution.
与此同时，片上系统的测试问题也随之产生，基于边界扫描的内建自测试技术为片上系统的测试提供了新的解决方案。
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