The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.

采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。

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The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.

采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。

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