However, there is information embedded in these design artifacts that describe a deeper level of granularity in the board itself: the traces that connect the components on the board.
但是在这些设计文档里面嵌入了一些信息，而这些信息表达了板子更深的粒度信息：板子上连接元件的轨迹。
To resolve them, two design methods of board level dynamic BS chain based on boundary scan technology are proposed in this paper.
为了解决上述问题，文中提出了两种基于边界扫描技术的板级动态链路设计方法。
The IBIS model is used to help get exact information in the integrity constraint design of system board level or multiple board level signals for analysis and calculation.
IBIS模型可以帮助设计者在系统板级或多板信号完整性约束的设计中获取准确的信息，以进行分析和计算。
The device's WLCSP (Wafer Level Chip Scale Package) is ultra compact, simplifying board design.
该器件的WLCSP(晶圆级芯片尺寸封装)是超小型，简化电路板设计。
To effectively reduce the injection-machine mould-board weight, sequential optimization design method starting from high level topology optimization to low level parameter optimization was proposed.
为了有效地降低注塑机模板的重量，提出了从高层次拓扑优化到底层次参数化优化的顺序优化设计方法。
If the pin assignments within the FPGA do not agree with the implemented design at the board level, damage can occur to either the FPGA component or the board-level circuits.
如果FPGA上的引脚分配与在电路板一级实现的设计不符的话，就会损坏fpga器件或电路板上的外围器件。
If the pin assignments within the FPGA do not agree with the implemented design at the board level, damage can occur to either the FPGA component or the board-level circuits.
如果FPGA上的引脚分配与在电路板一级实现的设计不符的话，就会损坏fpga器件或电路板上的外围器件。
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