Data may arrive at the FPGA receiver with channel -to -channel bit skew and word skew due to different trace length and smaller data window.

在高速数据传输接口中，由于数据窗缩小以及传输路径不一致，造成数据和时钟信号在FPGA的接收端发生位偏移和字偏移。

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Data may arrive at the FPGA receiver with channel -to -channel bit skew and word skew due to different trace length and smaller data window.

在高速数据传输接口中，由于数据窗缩小以及传输路径不一致，造成数据和时钟信号在FPGA的接收端发生位偏移和字偏移。

youdao