The paper introduce the circuit on conversing difference signal to TTL , and introduce in detail how to gained bit-clock signal .
本文主要详细讲述了如何利用差分变换后的波形提取位时钟信号。
A combination lock, a travel alarm clock, nail clippers, spare batteries for the camera and a bit of laundry soap are always needed, regardless of your destination.
无论你去哪，一个密码锁，一个旅游闹钟，指甲刀，相机的备用电池以及一些洗衣香皂，总是不可或缺的。
They're willing to set the alarm clock a bit early in order to capture the beauty of a sunrise so others can see.
他们乐意用闹钟早些唤醒自己，就是为了捕捉日出之美，这样其他人就能分享了。
A good rule of thumb is to encrypt on a 32-bit CPU at the rate of 10 CPU clock cycles per byte.
一个好的经验法则是在32位CPU上以每字节10个CPU时钟周期的速率加密。
Using binary notation, 26 movable bit levers inside each bit serial adder convert the swing from the pendulum into a visible notation on the clock.
使用二进制表示法，在每个26位串行加法器动产位的杠杆转换成一个钟摆在摆动的时钟可见符号。
After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse.
在收到停止位之后，设备将通过拉低数据线，生成最后一个时钟脉冲来应答收到的字节。
SCSI-1 defined an 8-bit parallel interface with a 5MHz data clock, providing a maximum data transfer rate of 5 megabytes per second (MB/s).
SCSI-1定义了一种具有5MHz数据时钟的8-bit并行接口，能提供最高 5 兆字节每秒（5MB/s）的数据传输速率。
It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.
这就是移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器会移动一位。
Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
So we don't know if a short sleeper can live longer by extending their sleep and we don't know if a long sleeper can live longer by setting the alarm clock a bit earlier.
也就是说我们不清楚如果一个睡眠不足的人是否可以通过增加睡眠时间来活的更久，也不清楚是否一个睡的太多的人是否可以通过把他们的闹钟调早一些就可以更长寿。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
Through controlling an N-bit accumulator and then get its highest bit to generate the programmable clock.
通过控制一个N位累加器累加，取其最高位，即可得到可编程时钟源。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port.
它内置一个低功耗、高速、16位不失码的采样adc、一个内部转换时钟和一个多功能串行接口。
The control system includes a first counter which performs a bit count according to provided channel bit clock signals;
该控制系统包括第一计数器，依据一提供的频道位时钟脉冲信号执行位计数；
This paper presents a clock control circuit in which an electronic clock is made by a MCU AT89C2051 16-bit timer and real-time control is achieved by the electronic clock's function of precise timing.
提出的时钟控制电路，是利用单片机at89c 2051的16位定时器做成电子时钟，并利用电子时钟的精确定时作用实现了实时控制。
Additionaly, by using of 16-bit counters and external 2mhz clock signal, the distinguishability of the control Angle is increased.
又因采用外加2m时钟作为计时信号，提高了控制角的分辨率。
Every time you tell a lie, the hands on your clock will move a tiny bit.
他每扯一次谎时钟的指针就动一小格。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
So we don't know if a short sleeper can live longer by extending their sleep, and we don't know if a long sleeper can live longer by setting the alarm clock a bit earlier.
因此我们也不知道延长一个睡眠时间太短的人的睡眠时间是否能延长他的寿命，或者让睡眠时间太长的人把闹铃调早些。
It is most startling to hear a watch or clock clicking away the seconds, each click indicating the shortening of one's life by a little bit.
最令人触目惊心的一件事，是看着钟表上的秒针一下一下的移动，每移动一下就是表示我们的寿命已经缩短了一部分。
How soon did I know you on earth, long or short? I feel a little bit trance, as it was 12 o 'clock of dial in the polar day, midday or midnight, it's hard to judge.
认识你到底有多长时间，漫长还是短暂？我感到恍惚，像是极昼之中看到表盘上的12点，无法判断是在正午还是子夜。
If you ate a light, healthy, lunch, you may well be feeling a bit peckish by 4 o 'clock.
如果你吃了顿清淡的，健康的午餐，到下午四点的时候，你也会觉得有些饿。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
It consists of an 8-bit 6502 CPU (without support for decimal mode, also known as BCD), DMA transfer unit, pseudo audio processing unit, 1/12 clock divider, and a bit of logic for address decoding.
他由一个8位6502CPU（不支持整数模式，也被称为BCD），DMA传输单元，伪音频处理单元，1/12时钟分频器，以及1位逻辑单位的地址译码。
It consists of an 8-bit 6502 CPU (without support for decimal mode, also known as BCD), DMA transfer unit, pseudo audio processing unit, 1/12 clock divider, and a bit of logic for address decoding.
他由一个8位6502CPU（不支持整数模式，也被称为BCD），DMA传输单元，伪音频处理单元，1/12时钟分频器，以及1位逻辑单位的地址译码。
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