However, as the design rule continuously shrank down beyond the 45 nm, conventional planar CMOS devices encounter significant challenges.

不过，当设计规章向45奈米以下持续缩小时，传统的平面的电晶体将遇到很多显著的挑战。

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However, as the design rule continuously shrank down beyond the 45 nm, conventional planar CMOS devices encounter significant challenges.

不过，当设计规章向45奈米以下持续缩小时，传统的平面的电晶体将遇到很多显著的挑战。

youdao