This paper presents an automatic design method for a carry save array multiplier with arbitrary number of bits.
本文给出一种任意多位的保留进位阵列乘法器的自动设计方法。
The direct 2's complement array multiplier principle of work is "Computer Organization Principle" the curriculum difficulty.
直接补码阵列乘法器的工作原理是《计算机组成原理》课程的难点。
Therefore, if each array element is 8 bytes long, you can use 8 as a multiplier.
因此，如果每个数组元素的长度都是8个字节，那么我们就可以使用8作为倍数。
In summing of the last product in the traditional multiplier design, the array or iteration summing method is used, which is not suitable to the design of small or middle scale integration circuit.
传统的乘法器的设计，在最终的乘积项求和时，常采用阵列相加或叠代相加的方法，不适用中小规模的微处理器的设计。
The designed multiplier has only 9 partial products, which effectively reduces the size and delay of compression array.
设计完成的乘法器只产生9个部分积，有效降低了部分积压缩阵列的规模与延时。
The designed multiplier has only 9 partial products, which effectively reduces the size and delay of compression array.
设计完成的乘法器只产生9个部分积，有效降低了部分积压缩阵列的规模与延时。
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